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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: test_bench_top.v,v 1.10 2003-09-23 13:09:25 markom Exp $
//
//  $Date: 2003-09-23 13:09:25 $
//  $Revision: 1.10 $
//  $Author: markom $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.9  2003/08/22 07:12:31  rherveille
//               Enabled Fifo Underrun test
//
//               Revision 1.8  2003/05/07 14:39:19  rherveille
//               Added DVI tests
//
//               Revision 1.7  2003/05/07 09:45:28  rherveille
//               Numerous updates and added checks
//
//               Revision 1.6  2003/03/19 17:22:19  rherveille
//               Added WISHBONE revB.3 sanity checks
//
//               Revision 1.5  2003/03/19 12:20:53  rherveille
//               Changed timing section in VGA core, changed testbench accordingly.
//               Fixed bug in 'timing check' test.
//
//               Revision 1.4  2002/02/07 05:38:32  rherveille
//               Added wb_ack delay section to testbench
//
//
//
//
//
 
`timescale 1ns/10ps
 
module test;
 
reg             clk;
reg             rst;
 
parameter       LINE_FIFO_AWIDTH = 7;
 
wire            int;
wire    [31:0]   wb_addr_o;
wire    [31:0]   wb_data_i;
wire    [31:0]   wb_data_o;
wire    [3:0]    wb_sel_o;
wire            wb_we_o;
wire            wb_stb_o;
wire            wb_cyc_o;
wire    [2:0]    wb_cti_o;
wire    [1:0]    wb_bte_o;
wire            wb_ack_i;
wire            wb_err_i;
wire    [31:0]   wb_addr_i;
wire    [31:0]   wbm_data_i;
wire    [3:0]    wb_sel_i;
wire            wb_we_i;
wire            wb_stb_i;
wire            wb_cyc_i;
wire            wb_ack_o;
wire            wb_rty_o;
wire            wb_err_o;
reg             pclk_i;
wire            pclk;
wire            hsync;
wire            vsync;
wire            ihsync;
wire            ivsync;
wire            csync;
wire            blanc;
wire    [7:0]    red;
wire    [7:0]    green;
wire    [7:0]    blue;
wire            dvi_de_o;
`ifdef VGA_12BIT_DVI
wire    [11:0]   dvi_d_o;
`else
wire    [23:0]   dvi_d_o;
`endif
 
wire vga_stb_i;
wire clut_stb_i;
 
reg             scen;
 
// Test Bench Variables
integer         wd_cnt;
integer         error_cnt;
 
// Misc Variables
reg     [31:0]   data;
reg     [31:0]   pattern;
reg             int_warn;
 
integer         n;
integer         mode;
 
reg     [7:0]    thsync, thgdel;
reg     [15:0]   thgate, thlen;
reg     [7:0]    tvsync, tvgdel;
reg     [15:0]   tvgate, tvlen;
reg             hpol;
reg             vpol;
reg             cpol;
reg             bpol;
integer         p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [1:0]    cd;
reg             pc;
reg     [31:0]   vbase;
reg     [31:0]   cbase;
reg     [31:0]   vbara;
reg     [31:0]   vbarb;
reg     [7:0]    bank;
 
/////////////////////////////////////////////////////////////////////
//
// Defines
//
 
`define CTRL            32'h0000_0000
`define STAT            32'h0000_0004
`define HTIM            32'h0000_0008
`define VTIM            32'h0000_000c
`define HVLEN           32'h0000_0010
`define VBARA           32'h0000_0014
`define VBARB           32'h0000_0018
 
`define USE_VC          1
 
parameter       PCLK_C = 30;
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
initial
   begin
        $timeformat (-9, 1, " ns", 12);
        $display("\n\n");
        $display("******************************************************");
        $display("* WISHBONE VGA/LCD Controller Simulation started ... *");
        $display("******************************************************");
        $display("\n");
`ifdef WAVES
        $shm_open("waves");
        $shm_probe("AS",test,"AS");
        $display("INFO: Signal dump enabled ...\n\n");
`endif
        scen = 0;
        error_cnt = 0;
        clk = 0;
        pclk_i = 0;
        rst = 0;
        int_warn=1;
 
        repeat(20)      @(posedge clk);
        rst = 1;
        repeat(20)      @(posedge clk);
 
        // HERE IS WHERE THE TEST CASES GO ...
 
if(0)    // Full Regression Run
   begin
 
   end
else
if(1)   // Quick Regression Run
   begin
        reg_test;
        tim_test;
 
`ifdef VGA_24BIT_DVI
        dvi_pd_test;
`endif
`ifdef VGA_12BIT_DVI
`else
        pd1_test;
        pd2_test;
`endif
 
        ur_test;
   end
else
   begin
 
        //
        // TEST DEVELOPMENT AREA
        //
$display("\n\n");
$display("*****************************************************");
$display("*** XXX Test                                 ***");
$display("*****************************************************\n");
 
        s0.fill_mem(1);
 
        repeat(10) @(posedge clk);
 
        vbara = 32'h0000_0000;
        vbarb = 32'h0001_0000;
 
        m0.wb_wr1( `VBARA, 4'hf, vbara );
        m0.wb_wr1( `VBARB, 4'hf, vbarb );
 
        thsync = 0;
        thgdel = 0;
        thgate = 340;
        thlen = 345;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 240;
        tvlen = 245;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
mode = 2;
 
//for(mode=0;mode<1;mode=mode+1)
for(bank=0;bank<3;bank=bank + 1)
   begin
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                2'h0,   // VBL
                                1'b0,   // Reserved
                                1'b1,   // CBSWE
                                1'b1,   // VBSWE
                                1'b0,   // BSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        $display("Mode: %0d Screen: %0d", mode, bank);
        //repeat(2) @(posedge vsync);
        @(posedge vsync);
 
        // For Each Line
        for(l=0;l<tvgate+1;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(blanc)    @(posedge pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                if(bank[0])      vbase = vbarb[31:2];
                else            vbase = vbara[31:2];
                if(bank[0])      cbase = 32'h0000_0c00;
                else            cbase = 32'h0000_0800;
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                case(mode)
                   0:    // 24 bit/pixel mode
                   begin
                        pra = pn[31:2] * 3;     // Pixel relative Address
                        paa = pra + vbase;              // Pixel Absolute Address
 
                        // Pixel Data
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = tmp[31:8];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd[23:16] = tmp[7:0];
                                tmp = s0.mem[paa+1];
                                pd[15:0] = tmp[31:16];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa+1];
                                pd[23:8] = tmp[15:0];
                                tmp = s0.mem[paa+2];
                                pd[7:0] = tmp[31:24];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa+2];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   1:   // 8 bit/pixel grayscale mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                             end
                        endcase
                   end
 
                   2:   // 8 bit/pixel Pseudo Color mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[31:24]];
                                pd = tmp[23:0];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[23:16]];
                                pd = tmp[23:0];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[15:8]];
                                pd = tmp[23:0];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[7:0]];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   3:   // 16 bit/pixel mode
                   begin
                        pra = pn[31:1];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp[15:0] = tmp[31:16];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                        endcase
                   end
 
                endcase
 
                if(pd !== {red, green, blue} )
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
                                pd, red, green, blue);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                   end
 
                @(posedge pclk);
 
           end
   end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
 
   end
 
        repeat(10)      @(posedge clk);
        $finish;
   end
 
/////////////////////////////////////////////////////////////////////
//
// Sync Monitor
//
 
`ifdef VGA_12BIT_DVI
sync_check #(PCLK_C) ucheck(
`else
sync_check #(PCLK_C) ucheck(
`endif
                .pclk(          pclk            ),
                .rst(           rst             ),
                .enable(        scen            ),
                .hsync(         hsync           ),
                .vsync(         vsync           ),
                .csync(         csync           ),
                .blanc(         blanc           ),
                .hpol(          hpol            ),
                .vpol(          vpol            ),
                .cpol(          cpol            ),
                .bpol(          bpol            ),
                .thsync(        thsync          ),
                .thgdel(        thgdel          ),
                .thgate(        thgate          ),
                .thlen(         thlen           ),
                .tvsync(        tvsync          ),
                .tvgdel(        tvgdel          ),
                .tvgate(        tvgate          ),
                .tvlen(         tvlen           ) );
 
/////////////////////////////////////////////////////////////////////
//
// Video Data Monitor
//
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE revB.3 checker
//
 
wb_b3_check u_wb_check (
        .clk_i ( clk      ),
        .cyc_i ( wb_cyc_o ),
        .stb_i ( wb_stb_o ),
        .cti_i ( wb_cti_o ),
        .bte_i ( wb_bte_o ),
        .we_i  ( wb_we_o  ),
        .ack_i ( wb_ack_i ),
        .err_i ( wb_err_i ),
        .rty_i ( 1'b0     ) );
 
 
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
 
always @(posedge clk)
        if(wb_cyc_i | wb_cyc_o | wb_ack_i | wb_ack_o | hsync)
          wd_cnt <= #1 0;
        else
          wd_cnt <= #1 wd_cnt + 1;
 
 
always @(wd_cnt)
        if(wd_cnt>9000)
           begin
                $display("\n\n*************************************\n");
                $display("ERROR: Watch Dog Counter Expired\n");
                $display("*************************************\n\n\n");
                $finish;
           end
 
 
always @(posedge int)
  if(int_warn)
   begin
        $display("\n\n*************************************\n");
        $display("WARNING: Recieved Interrupt (%0t)", $time);
        $display("*************************************\n\n\n");
   end
 
always #2.4 clk = ~clk;
always #(PCLK_C/2) pclk_i = ~pclk_i;
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE VGA/LCD IP Core
//
 
 
// Module Prototype
 
`ifdef VGA_12BIT_DVI
vga_dvi_top #(1'b0, LINE_FIFO_AWIDTH) u0 (
`else
vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 (
`endif
                .wb_clk_i     ( clk             ),
                .wb_rst_i     ( 1'b0            ),
                .rst_i        ( rst             ),
                .wb_inta_o    ( int             ),
 
                //-- slave signals
                .wbs_adr_i    ( wb_addr_i[11:0] ),
                .wbs_dat_i    ( wb_data_i       ),
                .wbs_dat_o    ( wb_data_o       ),
                .wbs_sel_i    ( wb_sel_i        ),
                .wbs_we_i     ( wb_we_i         ),
                .wbs_stb_i    ( wb_stb_i        ),
                .wbs_cyc_i    ( wb_cyc_i        ),
                .wbs_ack_o    ( wb_ack_o        ),
                .wbs_rty_o    ( wb_rty_o        ),
                .wbs_err_o    ( wb_err_o        ),
 
                //-- master signals
                .wbm_adr_o    ( wb_addr_o[31:0] ),
                .wbm_dat_i    ( wbm_data_i      ),
                .wbm_sel_o    ( wb_sel_o        ),
                .wbm_we_o     ( wb_we_o         ),
                .wbm_stb_o    ( wb_stb_o        ),
                .wbm_cyc_o    ( wb_cyc_o        ),
                .wbm_cti_o    ( wb_cti_o        ),
                .wbm_bte_o    ( wb_bte_o        ),
                .wbm_ack_i    ( wb_ack_i        ),
                .wbm_err_i    ( wb_err_i        ),
 
                //-- VGA signals
                .clk_p_i      ( pclk_i          )
        `ifdef VGA_24BIT_DVI
              , .dvi_hsync_o  ( ihsync          ),
                .dvi_vsync_o  ( ivsync          ),
                .dvi_de_o     ( dvi_de_o        ),
                .dvi_d_o      ( dvi_d_o         )
        `endif
        `ifdef VGA_12BIT_DVI
        `else
              , .hsync_pad_o  ( hsync           ),
                .vsync_pad_o  ( vsync           ),
                .csync_pad_o  ( csync           ),
                .blank_pad_o  ( blanc           ),
                .r_pad_o      ( red             ),
                .g_pad_o      ( green           ),
                .b_pad_o      ( blue            )
        `endif
 
        `ifdef VGA_BIST
                /* BIST signals */
              , .scanb_rst(1'b1),
                .scanb_clk(1'b0),
                .scanb_si (1'b0),
                .scanb_en (1'b0),
                .scanb_so ()
        `endif
        );
 
assign pclk = pclk_i;
 
`ifdef VGA_12BIT_DVI
assign hsync = !ihsync;
assign vsync = !ivsync;
`endif
 
wb_mast m0(     .clk(           clk             ),
                .rst(           rst             ),
                .adr(           wb_addr_i       ),
                .din(           wb_data_o       ),
                .dout(          wb_data_i       ),
                .cyc(           wb_cyc_i        ),
                .stb(           wb_stb_i        ),
                .sel(           wb_sel_i        ),
                .we(            wb_we_i         ),
                .ack(           wb_ack_o        ),
                .err(           wb_err_o        ),
                .rty(           1'b0            )
                );
 
wb_slv #(24) s0(.clk(           clk             ),
                .rst(           rst             ),
                .adr(           {1'b0, wb_addr_o[30:0]}  ),
                .din(           32'h0           ),
                .dout(          wbm_data_i      ),
                .cyc(           wb_cyc_o        ),
                .stb(           wb_stb_o        ),
                .sel(           wb_sel_o        ),
                .we(            wb_we_o         ),
                .ack(           wb_ack_i        ),
                .err(           wb_err_i        ),
                .rty(                           )
                );
 
`include "tests.v"
 
endmodule

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Top Level Test Bench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	60	markom	`// $Id: test_bench_top.v,v 1.10 2003-09-23 13:09:25 markom Exp $`
41	16	rudi	`//`
42	60	markom	`// $Date: 2003-09-23 13:09:25 $`
43			`// $Revision: 1.10 $`
44			`// $Author: markom $`
45	16	rudi	`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	60	markom	`// Revision 1.9 2003/08/22 07:12:31 rherveille`
51			`// Enabled Fifo Underrun test`
52			`//`
53	58	rherveille	`// Revision 1.8 2003/05/07 14:39:19 rherveille`
54			`// Added DVI tests`
55			`//`
56	54	rherveille	`// Revision 1.7 2003/05/07 09:45:28 rherveille`
57			`// Numerous updates and added checks`
58			`//`
59	52	rherveille	`// Revision 1.6 2003/03/19 17:22:19 rherveille`
60			`// Added WISHBONE revB.3 sanity checks`
61			`//`
62	46	rherveille	`// Revision 1.5 2003/03/19 12:20:53 rherveille`
63			`// Changed timing section in VGA core, changed testbench accordingly.`
64			`// Fixed bug in 'timing check' test.`
65			`//`
66	44	rherveille	`// Revision 1.4 2002/02/07 05:38:32 rherveille`
67			`// Added wb_ack delay section to testbench`
68	16	rudi	`//`
69			`//`
70			`//`
71	44	rherveille	`//`
72	52	rherveille	`//`
73	16	rudi
74	44	rherveille	`timescale 1ns/10ps
75	16	rudi
76			`module test;`
77
78			`reg clk;`
79			`reg rst;`
80
81			`parameter LINE_FIFO_AWIDTH = 7;`
82
83			`wire int;`
84			`wire [31:0] wb_addr_o;`
85			`wire [31:0] wb_data_i;`
86			`wire [31:0] wb_data_o;`
87			`wire [3:0] wb_sel_o;`
88			`wire wb_we_o;`
89			`wire wb_stb_o;`
90			`wire wb_cyc_o;`
91	46	rherveille	`wire [2:0] wb_cti_o;`
92			`wire [1:0] wb_bte_o;`
93	16	rudi	`wire wb_ack_i;`
94			`wire wb_err_i;`
95			`wire [31:0] wb_addr_i;`
96			`wire [31:0] wbm_data_i;`
97			`wire [3:0] wb_sel_i;`
98			`wire wb_we_i;`
99			`wire wb_stb_i;`
100			`wire wb_cyc_i;`
101			`wire wb_ack_o;`
102	52	rherveille	`wire wb_rty_o;`
103	16	rudi	`wire wb_err_o;`
104	52	rherveille	`reg pclk_i;`
105			`wire pclk;`
106	60	markom	`wire hsync;`
107	16	rudi	`wire vsync;`
108	60	markom	`wire ihsync;`
109			`wire ivsync;`
110	16	rudi	`wire csync;`
111			`wire blanc;`
112			`wire [7:0] red;`
113			`wire [7:0] green;`
114			`wire [7:0] blue;`
115	52	rherveille	`wire dvi_de_o;`
116	60	markom	`ifdef VGA_12BIT_DVI
117	52	rherveille	`wire [11:0] dvi_d_o;`
118	60	markom	`else
119			`wire [23:0] dvi_d_o;`
120			`endif
121	16	rudi
122	24	rherveille	`wire vga_stb_i;`
123			`wire clut_stb_i;`
124	16	rudi
125			`reg scen;`
126
127			`// Test Bench Variables`
128			`integer wd_cnt;`
129			`integer error_cnt;`
130
131			`// Misc Variables`
132			`reg [31:0] data;`
133			`reg [31:0] pattern;`
134			`reg int_warn;`
135
136			`integer n;`
137			`integer mode;`
138
139			`reg [7:0] thsync, thgdel;`
140			`reg [15:0] thgate, thlen;`
141			`reg [7:0] tvsync, tvgdel;`
142			`reg [15:0] tvgate, tvlen;`
143			`reg hpol;`
144			`reg vpol;`
145			`reg cpol;`
146			`reg bpol;`
147			`integer p, l;`
148			`reg [31:0] pn;`
149			`reg [31:0] pra, paa, tmp;`
150			`reg [23:0] pd;`
151			`reg [1:0] cd;`
152			`reg pc;`
153			`reg [31:0] vbase;`
154			`reg [31:0] cbase;`
155			`reg [31:0] vbara;`
156			`reg [31:0] vbarb;`
157			`reg [7:0] bank;`
158
159			`/////////////////////////////////////////////////////////////////////`
160			`//`
161	52	rherveille	`// Defines`
162	16	rudi	`//`
163
164			`define CTRL 32'h0000_0000
165			`define STAT 32'h0000_0004
166			`define HTIM 32'h0000_0008
167			`define VTIM 32'h0000_000c
168			`define HVLEN 32'h0000_0010
169			`define VBARA 32'h0000_0014
170			`define VBARB 32'h0000_0018
171
172			`define USE_VC 1
173
174	58	rherveille	`parameter PCLK_C = 30;`
175	24	rherveille
176	16	rudi	`/////////////////////////////////////////////////////////////////////`
177			`//`
178			`// Simulation Initialization and Start up Section`
179			`//`
180
181			`initial`
182			`begin`
183			`$timeformat (-9, 1, " ns", 12);`
184			`$display("\n\n");`
185			`$display("******************************************************");`
186			`$display("* WISHBONE VGA/LCD Controller Simulation started ... *");`
187			`$display("******************************************************");`
188			`$display("\n");`
189			`ifdef WAVES
190			`$shm_open("waves");`
191			`$shm_probe("AS",test,"AS");`
192			`$display("INFO: Signal dump enabled ...\n\n");`
193			`endif
194			`scen = 0;`
195			`error_cnt = 0;`
196			`clk = 0;`
197	52	rherveille	`pclk_i = 0;`
198	16	rudi	`rst = 0;`
199			`int_warn=1;`
200
201			`repeat(20) @(posedge clk);`
202			`rst = 1;`
203			`repeat(20) @(posedge clk);`
204
205			`// HERE IS WHERE THE TEST CASES GO ...`
206
207			`if(0) // Full Regression Run`
208			`begin`
209
210			`end`
211			`else`
212			`if(1) // Quick Regression Run`
213			`begin`
214	58	rherveille	`reg_test;`
215			`tim_test;`
216	29	rherveille
217	60	markom	`ifdef VGA_24BIT_DVI
218			`dvi_pd_test;`
219			`endif
220			`ifdef VGA_12BIT_DVI
221			`else
222	58	rherveille	`pd1_test;`
223			`pd2_test;`
224	54	rherveille	`endif
225	29	rherveille
226	58	rherveille	`ur_test;`
227	16	rudi	`end`
228			`else`
229			`begin`
230
231			`//`
232			`// TEST DEVELOPMENT AREA`
233			`//`
234			`$display("\n\n");`
235			`$display("*****************************************************");`
236			`$display("* XXX Test *");`
237			`$display("*****************************************************\n");`
238
239			`s0.fill_mem(1);`
240
241	52	rherveille	`repeat(10) @(posedge clk);`
242	16	rudi
243			`vbara = 32'h0000_0000;`
244			`vbarb = 32'h0001_0000;`
245
246			m0.wb_wr1( `VBARA, 4'hf, vbara );
247			m0.wb_wr1( `VBARB, 4'hf, vbarb );
248
249			`thsync = 0;`
250			`thgdel = 0;`
251			`thgate = 340;`
252			`thlen = 345;`
253
254			`tvsync = 0;`
255			`tvgdel = 0;`
256			`tvgate = 240;`
257			`tvlen = 245;`
258
259			`/*`
260			`thsync = 0;`
261			`thgdel = 0;`
262			`thgate = 63;`
263			`thlen = 70;`
264
265			`tvsync = 0;`
266			`tvgdel = 0;`
267			`tvgate = 32;`
268			`tvlen = 36;`
269			`*/`
270
271			`hpol = 0;`
272			`vpol = 0;`
273			`cpol = 0;`
274			`bpol = 0;`
275
276			m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
277			m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
278			m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
279
280			`mode = 2;`
281
282			`//for(mode=0;mode<1;mode=mode+1)`
283			`for(bank=0;bank<3;bank=bank + 1)`
284			`begin`
285			`case(mode)`
286			`0:`
287			`begin`
288			`cd = 2'h2;`
289			`pc = 1'b0;`
290			`end`
291			`1:`
292			`begin`
293			`cd = 2'h0;`
294			`pc = 1'b0;`
295			`end`
296			`2:`
297			`begin`
298			`cd = 2'h0;`
299			`pc = 1'b1;`
300			`end`
301			`3:`
302			`begin`
303			`cd = 2'h1;`
304			`pc = 1'b0;`
305			`end`
306			`endcase`
307
308			m0.wb_wr1( `CTRL, 4'hf, {
309			`16'h0, // Reserved`
310			`bpol, cpol,`
311			`vpol, hpol,`
312			`pc, // 1'b0, // PC`
313			`cd, // 2'h2, // CD`
314			`2'h0, // VBL`
315			`1'b0, // Reserved`
316			`1'b1, // CBSWE`
317			`1'b1, // VBSWE`
318			`1'b0, // BSIE`
319			`1'b0, // HIE`
320			`1'b0, // VIE`
321			`1'b1 // Video Enable`
322			`});`
323
324			`$display("Mode: %0d Screen: %0d", mode, bank);`
325			`//repeat(2) @(posedge vsync);`
326			`@(posedge vsync);`
327
328			`// For Each Line`
329			`for(l=0;l<tvgate+1;l=l+1)`
330			`// For each Pixel`
331			`for(p=0;p<thgate+1;p=p+1)`
332			`begin`
333			`while(blanc) @(posedge pclk); // wait for viewable data`
334
335			`//$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);`
336
337			`if(bank[0]) vbase = vbarb[31:2];`
338			`else vbase = vbara[31:2];`
339	24	rherveille	`if(bank[0]) cbase = 32'h0000_0c00;`
340			`else cbase = 32'h0000_0800;`
341	16	rudi
342			`// Depending on Mode, determine pixel data`
343			`// pixel number = line * (thgate + 1) + p`
344			`pn = l * (thgate + 1) + p;`
345
346			`case(mode)`
347			`0: // 24 bit/pixel mode`
348			`begin`
349			`pra = pn[31:2] * 3; // Pixel relative Address`
350			`paa = pra + vbase; // Pixel Absolute Address`
351
352			`// Pixel Data`
353			`case(pn[1:0])`
354			`0:`
355			`begin`
356			`tmp = s0.mem[paa];`
357			`pd = tmp[31:8];`
358			`end`
359			`1:`
360			`begin`
361			`tmp = s0.mem[paa];`
362			`pd[23:16] = tmp[7:0];`
363			`tmp = s0.mem[paa+1];`
364			`pd[15:0] = tmp[31:16];`
365			`end`
366			`2:`
367			`begin`
368			`tmp = s0.mem[paa+1];`
369			`pd[23:8] = tmp[15:0];`
370			`tmp = s0.mem[paa+2];`
371			`pd[7:0] = tmp[31:24];`
372			`end`
373			`3:`
374			`begin`
375			`tmp = s0.mem[paa+2];`
376			`pd = tmp[23:0];`
377			`end`
378			`endcase`
379			`end`
380
381			`1: // 8 bit/pixel grayscale mode`
382			`begin`
383			`pra = pn[31:2]; // Pixel relative Address`
384			`paa = pra + vbase; // Pixel Absolute Address`
385			`case(pn[1:0])`
386			`0:`
387			`begin`
388			`tmp = s0.mem[paa];`
389			`pd = { tmp[31:24], tmp[31:24], tmp[31:24] };`
390			`end`
391			`1:`
392			`begin`
393			`tmp = s0.mem[paa];`
394			`pd = { tmp[23:16], tmp[23:16], tmp[23:16] };`
395			`end`
396			`2:`
397			`begin`
398			`tmp = s0.mem[paa];`
399			`pd = { tmp[15:8], tmp[15:8], tmp[15:8] };`
400			`end`
401			`3:`
402			`begin`
403			`tmp = s0.mem[paa];`
404			`pd = { tmp[7:0], tmp[7:0], tmp[7:0] };`
405			`end`
406			`endcase`
407			`end`
408
409			`2: // 8 bit/pixel Pseudo Color mode`
410			`begin`
411			`pra = pn[31:2]; // Pixel relative Address`
412			`paa = pra + vbase; // Pixel Absolute Address`
413			`case(pn[1:0])`
414			`0:`
415			`begin`
416			`tmp = s0.mem[paa];`
417			`tmp = s0.mem[cbase[31:2] + tmp[31:24]];`
418			`pd = tmp[23:0];`
419			`end`
420			`1:`
421			`begin`
422			`tmp = s0.mem[paa];`
423			`tmp = s0.mem[cbase[31:2] + tmp[23:16]];`
424			`pd = tmp[23:0];`
425			`end`
426			`2:`
427			`begin`
428			`tmp = s0.mem[paa];`
429			`tmp = s0.mem[cbase[31:2] + tmp[15:8]];`
430			`pd = tmp[23:0];`
431			`end`
432			`3:`
433			`begin`
434			`tmp = s0.mem[paa];`
435			`tmp = s0.mem[cbase[31:2] + tmp[7:0]];`
436			`pd = tmp[23:0];`
437			`end`
438			`endcase`
439			`end`
440
441			`3: // 16 bit/pixel mode`
442			`begin`
443			`pra = pn[31:1]; // Pixel relative Address`
444			`paa = pra + vbase; // Pixel Absolute Address`
445			`case(pn[0])`
446			`0:`
447			`begin`
448			`tmp = s0.mem[paa];`
449			`tmp[15:0] = tmp[31:16];`
450			`pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};`
451			`end`
452			`1:`
453			`begin`
454			`tmp = s0.mem[paa];`
455			`pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};`
456			`end`
457			`endcase`
458			`end`
459
460			`endcase`
461
462			`if(pd !== {red, green, blue} )`
463			`begin`
464			`$display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",`
465			`pd, red, green, blue);`
466			`$display(" pixel=%0d, line=%0d, (%0t)",p,l,$time);`
467			`error_cnt = error_cnt + 1;`
468			`end`
469
470			`@(posedge pclk);`
471
472	46	rherveille	`end`
473	16	rudi	`end`
474
475			`show_errors;`
476			`$display("*****************************************************");`
477			`$display("* Test DONE ... *");`
478			`$display("*****************************************************\n\n");`
479
480
481			`end`
482
483			`repeat(10) @(posedge clk);`
484			`$finish;`
485			`end`
486
487			`/////////////////////////////////////////////////////////////////////`
488			`//`
489			`// Sync Monitor`
490			`//`
491
492	52	rherveille	`ifdef VGA_12BIT_DVI
493	60	markom	`sync_check #(PCLK_C) ucheck(`
494	52	rherveille	`else
495	46	rherveille	`sync_check #(PCLK_C) ucheck(`
496	52	rherveille	`endif
497	16	rudi	`.pclk( pclk ),`
498			`.rst( rst ),`
499			`.enable( scen ),`
500			`.hsync( hsync ),`

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