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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [generic_spram.v] - Blame information for rev 62

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides a behavioral model of generic    ////
////  single-port synchronous RAM.                                ////
////  It also contains a synthesizeable model for FPGAs.          ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Generic FPGA (VENDOR_FPGA)                                ////
////    Tested RAMs: Altera, Xilinx                               ////
////    Synthesis tools: LeonardoSpectrum, Synplicity             ////
////  - Xilinx (VENDOR_XILINX)                                    ////
////  - Altera (VENDOR_ALTERA)                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Richard Herveille, richard@asics.ws                   ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
`include "timescale.v"
 
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
 
module generic_spram(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
        //
        // Default address and data buses width
        //
        parameter aw = 6; //number of address-bits
        parameter dw = 8; //number of data-bits
 
        //
        // Generic synchronous single-port RAM interface
        //
        input           clk;  // Clock, rising edge
        input           rst;  // Reset, active high
        input           ce;   // Chip enable input, active high
        input           we;   // Write enable input, active high
        input           oe;   // Output enable input, active high
        input  [aw-1:0] addr; // address bus inputs
        input  [dw-1:0] di;   // input data bus
        output [dw-1:0] do;   // output data bus
 
        //
        // Module body
        //
 
`ifdef VENDOR_FPGA
        //
        // Instantiation synthesizeable FPGA memory
        //
        // This code has been tested using LeonardoSpectrum and Synplicity.
        // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
        //
 
        // NOTE:
        // 'synthesis syn_ramstyle="block_ram"' is a Synplify attribute.
        // It instructs Synplify to map to BlockRAMs instead of the default SelectRAMs
 
        reg [dw-1:0] mem [(1<<aw) -1:0] /* synthesis syn_ramstyle="block_ram" */;
        reg [aw-1:0] ra;
 
        // read operation
        always @(posedge clk)
          if (ce)
            ra <= #1 addr;     // read address needs to be registered to read clock
 
        assign #1 do = mem[ra];
 
        // write operation
        always @(posedge clk)
          if (we && ce)
            mem[addr] <= #1 di;
`else
 
`ifdef VENDOR_XILINX
 
        wire [dw-1:0] q;  // output from xilinx ram
        //
        // Instantiation of FPGA memory:
        //
        // Virtex/Spartan2 BlockRAMs
        //
        xilinx_ram_sp xilinx_ram(
                .clk(clk),
                .rst(rst),
                .addr(addr),
                .di(di),
                .en(ce),
                .we(we),
                .do(do)
        );
 
        defparam
                xilinx_ram.dwidth = dw,
                xilinx_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ALTERA
 
        //
        // Instantiation of FPGA memory:
        //
        // Altera FLEX EABs
        //
 
        altera_ram_sp altera_ram(
                .inclock(clk),
                .address(addr),
                .data(di),
                .we(we && ce),
                .q(do)
        );
 
        defparam
                altera_ram.dwidth = dw,
                altera_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ARTISAN
 
        //
        // Instantiation of ASIC memory:
        //
        // Artisan Synchronous Single-Port RAM (ra1sh)
        //
        artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(
                .CLK(clk),
                .CEN(~ce),
                .WEN(~we),
                .A(addr),
                .D(di),
                .OEN(~oe),
                .Q(do)
        );
 
`else
 
`ifdef VENDOR_AVANT
 
        //
        // Instantiation of ASIC memory:
        //
        // Avant! Asynchronous Two-Port RAM
        //
        avant_atp avant_atp(
                .web(~we),
                .reb(),
                .oeb(~oe),
                .rcsb(),
                .wcsb(),
                .ra(addr),
                .wa(addr),
                .di(di),
                .do(do)
        );
 
`else
 
`ifdef VENDOR_VIRAGE
 
        //
        // Instantiation of ASIC memory:
        //
        // Virage Synchronous 1-port R/W RAM
        //
        virage_ssp virage_ssp(
                .clk(clk),
                .adr(addr),
                .d(di),
                .we(we),
                .oe(oe),
                .me(ce),
                .q(do)
        );
 
`else
 
`ifdef VENDOR_VIRTUALSILICON
 
        //
        // Instantiation of ASIC memory:
        //
        // Virtual Silicon Single-Port Synchronous SRAM
        //
        virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(
                .CK(clk),
                .ADR(addr),
                .DI(di),
                .WEN(~we),
                .CEN(~ce),
                .OEN(~oe),
                .DOUT(do)
        );
 
`else
 
        //
        // Generic single-port synchronous RAM model
        //
 
        //
        // Generic RAM's registers and wires
        //
        reg  [dw-1:0] mem [(1<<aw)-1:0];  // RAM content
        wire [dw-1:0] q;                 // RAM output
        reg  [aw-1:0] raddr;             // RAM read address
        //
        // Data output drivers
        //
        assign do = (oe) ? q : {dw{1'bz}};
 
        //
        // RAM read and write
        //
 
        // read operation
        always@(posedge clk)
        if (ce) // && !we)
                raddr <= #1 addr;    // read address needs to be registered to read clock
 
        assign #1 q = rst ? {dw{1'b0}} : mem[raddr];
 
        // write operation
        always@(posedge clk)
                if (ce && we)
                        mem[addr] <= #1 di;
 
 
`endif // !VIRTUALSILICON_SSP
`endif // !VIRAGE_SSP
`endif // !AVANT_ATP
`endif // !ARTISAN_SSP
`endif // !VENDOR_ALTERA
`endif // !VENDOR_XILINX
`endif // !VENDOR_FPGA
 
endmodule
 
 
//
// Black-box modules
//
 
`ifdef VENDOR_ALTERA
        module altera_ram_sp (
                address,
                inclock,
                we,
                data,
                q) /* synthesis black_box */;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input  [awidth -1:0] address;
                input                inclock;
                input                we;
                input  [dwidth -1:0] data;
                output [dwidth -1:0] q;
 
                // synopsis translate_off
                // exemplar translate_off
 
                syn_ram_irou #(
                        "UNUSED",
                        dwidth,
                        awidth,
                        1 << awidth
                )
                altera_spram_model (
                        .Inclock(inclock),
                        .Address(address),
                        .Data(data),
                        .WE(we),
                        .Q(q)
                );
 
                // exemplar translate_on
                // synopsis translate_on
 
        endmodule
`endif // VENDOR_ALTERA
 
`ifdef VENDOR_XILINX
        module xilinx_ram_sp (
                        clk,
                        rst,
                        addr,
                        di,
                        en,
                        we,
                        do) /* synthesis black_box */ ;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input                clk;
                input                rst;
                input  [awidth -1:0] addr;
                input  [dwidth -1:0] di;
                input                en;
                input                we;
                output [dwidth -1:0] do;
 
                // insert simulation model
 
 
                // synopsys translate_off
                // exemplar translate_off
 
                C_MEM_SP_BLOCK_V1_0 #(
                        awidth,
                        1,
                        "0",
                        1 << awidth,
                        1,
                        1,
                        1,
                        1,
                        1,
                        1,
                        1,
                        "",
                        16,
                        0,
                        0,
                        1,
                        1,
                        dwidth
                )
                xilinx_spram_model (
                        .CLK(clk),
                        .RST(rst),
                        .ADDR(addr),
                        .DI(di),
                        .EN(en),
                        .WE(we),
                        .DO(do)
                );
 
                // exemplar translate_on
                // synopsys translate_on
 
        endmodule
`endif // VENDOR_XILINX
 

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [generic_spram.v] - Blame information for rev 62

Line No.	Rev	Author	Line
1	17	rherveille	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides a behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It also contains a synthesizeable model for FPGAs. ////`
15			`//// It should be used in all OPENCORES designs that want to be ////`
16			`//// portable accross different target technologies and ////`
17			`//// independent of target memory. ////`
18			`//// ////`
19			`//// Supported ASIC RAMs are: ////`
20			`//// - Artisan Single-Port Sync RAM ////`
21			`//// - Avant! Two-Port Sync RAM (*) ////`
22			`//// - Virage Single-Port Sync RAM ////`
23			`//// - Virtual Silicon Single-Port Sync RAM ////`
24			`//// ////`
25			`//// Supported FPGA RAMs are: ////`
26			`//// - Generic FPGA (VENDOR_FPGA) ////`
27			`//// Tested RAMs: Altera, Xilinx ////`
28			`//// Synthesis tools: LeonardoSpectrum, Synplicity ////`
29			`//// - Xilinx (VENDOR_XILINX) ////`
30			`//// - Altera (VENDOR_ALTERA) ////`
31			`//// ////`
32			`//// To Do: ////`
33			`//// - fix avant! two-port ram ////`
34			`//// - add additional RAMs ////`
35			`//// ////`
36			`//// Author(s): ////`
37			`//// - Richard Herveille, richard@asics.ws ////`
38			`//// - Damjan Lampret, lampret@opencores.org ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//// ////`
42			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
43			`//// ////`
44			`//// This source file may be used and distributed without ////`
45			`//// restriction provided that this copyright statement is not ////`
46			`//// removed from the file and that any derivative work contains ////`
47			`//// the original copyright notice and the associated disclaimer. ////`
48			`//// ////`
49			`//// This source file is free software; you can redistribute it ////`
50			`//// and/or modify it under the terms of the GNU Lesser General ////`
51			`//// Public License as published by the Free Software Foundation; ////`
52			`//// either version 2.1 of the License, or (at your option) any ////`
53			`//// later version. ////`
54			`//// ////`
55			`//// This source is distributed in the hope that it will be ////`
56			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
57			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
58			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
59			`//// details. ////`
60			`//// ////`
61			`//// You should have received a copy of the GNU Lesser General ////`
62			`//// Public License along with this source; if not, download it ////`
63			`//// from http://www.opencores.org/lgpl.shtml ////`
64			`//// ////`
65			`//////////////////////////////////////////////////////////////////////`
66			`//`
67			`// CVS Revision History`
68			`//`
69			`// $Log: not supported by cvs2svn $`
70			`//`
71			`//`
72
73			`include "timescale.v"
74
75			//`define VENDOR_XILINX
76			//`define VENDOR_ALTERA
77	43	rherveille	`define VENDOR_FPGA
78	17	rherveille
79			`module generic_spram(`
80			`// Generic synchronous single-port RAM interface`
81			`clk, rst, ce, we, oe, addr, di, do`
82			`);`
83
84			`//`
85			`// Default address and data buses width`
86			`//`
87			`parameter aw = 6; //number of address-bits`
88			`parameter dw = 8; //number of data-bits`
89
90			`//`
91			`// Generic synchronous single-port RAM interface`
92			`//`
93			`input clk; // Clock, rising edge`
94			`input rst; // Reset, active high`
95			`input ce; // Chip enable input, active high`
96			`input we; // Write enable input, active high`
97			`input oe; // Output enable input, active high`
98			`input [aw-1:0] addr; // address bus inputs`
99			`input [dw-1:0] di; // input data bus`
100			`output [dw-1:0] do; // output data bus`
101
102			`//`
103			`// Module body`
104			`//`
105
106			`ifdef VENDOR_FPGA
107			`//`
108			`// Instantiation synthesizeable FPGA memory`
109			`//`
110			`// This code has been tested using LeonardoSpectrum and Synplicity.`
111			`// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.`
112			`//`
113
114	43	rherveille	`// NOTE:`
115			`// 'synthesis syn_ramstyle="block_ram"' is a Synplify attribute.`
116			`// It instructs Synplify to map to BlockRAMs instead of the default SelectRAMs`
117	17	rherveille
118	43	rherveille	`reg [dw-1:0] mem [(1<<aw) -1:0] /* synthesis syn_ramstyle="block_ram" */;`
119			`reg [aw-1:0] ra;`
120	17	rherveille
121	43	rherveille	`// read operation`
122			`always @(posedge clk)`
123			`if (ce)`
124			`ra <= #1 addr; // read address needs to be registered to read clock`
125	17	rherveille
126	43	rherveille	`assign #1 do = mem[ra];`
127
128			`// write operation`
129			`always @(posedge clk)`
130			`if (we && ce)`
131			`mem[addr] <= #1 di;`
132	17	rherveille	`else
133
134			`ifdef VENDOR_XILINX
135
136			`wire [dw-1:0] q; // output from xilinx ram`
137			`//`
138			`// Instantiation of FPGA memory:`
139			`//`
140			`// Virtex/Spartan2 BlockRAMs`
141			`//`
142			`xilinx_ram_sp xilinx_ram(`
143			`.clk(clk),`
144			`.rst(rst),`
145			`.addr(addr),`
146			`.di(di),`
147			`.en(ce),`
148			`.we(we),`
149			`.do(do)`
150			`);`
151
152			`defparam`
153			`xilinx_ram.dwidth = dw,`
154			`xilinx_ram.awidth = aw;`
155
156			`else
157
158			`ifdef VENDOR_ALTERA
159
160			`//`
161			`// Instantiation of FPGA memory:`
162			`//`
163			`// Altera FLEX EABs`
164			`//`
165
166			`altera_ram_sp altera_ram(`
167			`.inclock(clk),`
168			`.address(addr),`
169			`.data(di),`
170			`.we(we && ce),`
171			`.q(do)`
172			`);`
173
174			`defparam`
175			`altera_ram.dwidth = dw,`
176			`altera_ram.awidth = aw;`
177
178			`else
179
180			`ifdef VENDOR_ARTISAN
181
182			`//`
183			`// Instantiation of ASIC memory:`
184			`//`
185			`// Artisan Synchronous Single-Port RAM (ra1sh)`
186			`//`
187			`artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(`
188			`.CLK(clk),`
189			`.CEN(~ce),`
190			`.WEN(~we),`
191			`.A(addr),`
192			`.D(di),`
193			`.OEN(~oe),`
194			`.Q(do)`
195			`);`
196
197			`else
198
199			`ifdef VENDOR_AVANT
200
201			`//`
202			`// Instantiation of ASIC memory:`
203			`//`
204			`// Avant! Asynchronous Two-Port RAM`
205			`//`
206			`avant_atp avant_atp(`
207			`.web(~we),`
208			`.reb(),`
209			`.oeb(~oe),`
210			`.rcsb(),`
211			`.wcsb(),`
212			`.ra(addr),`
213			`.wa(addr),`
214			`.di(di),`
215			`.do(do)`
216			`);`
217
218			`else
219
220			`ifdef VENDOR_VIRAGE
221
222			`//`
223			`// Instantiation of ASIC memory:`
224			`//`
225			`// Virage Synchronous 1-port R/W RAM`
226			`//`
227			`virage_ssp virage_ssp(`
228			`.clk(clk),`
229			`.adr(addr),`
230			`.d(di),`
231			`.we(we),`
232			`.oe(oe),`
233			`.me(ce),`
234			`.q(do)`
235			`);`
236
237			`else
238
239			`ifdef VENDOR_VIRTUALSILICON
240
241			`//`
242			`// Instantiation of ASIC memory:`
243			`//`
244			`// Virtual Silicon Single-Port Synchronous SRAM`
245			`//`
246			`virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(`
247			`.CK(clk),`
248			`.ADR(addr),`
249			`.DI(di),`
250			`.WEN(~we),`
251			`.CEN(~ce),`
252			`.OEN(~oe),`
253			`.DOUT(do)`
254			`);`
255
256			`else
257
258			`//`
259			`// Generic single-port synchronous RAM model`
260			`//`
261
262			`//`
263			`// Generic RAM's registers and wires`
264			`//`
265			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
266			`wire [dw-1:0] q; // RAM output`
267			`reg [aw-1:0] raddr; // RAM read address`
268			`//`
269			`// Data output drivers`
270			`//`
271			`assign do = (oe) ? q : {dw{1'bz}};`
272
273			`//`
274			`// RAM read and write`
275			`//`
276
277			`// read operation`
278			`always@(posedge clk)`
279			`if (ce) // && !we)`
280			`raddr <= #1 addr; // read address needs to be registered to read clock`
281
282			`assign #1 q = rst ? {dw{1'b0}} : mem[raddr];`
283
284			`// write operation`
285			`always@(posedge clk)`
286			`if (ce && we)`
287			`mem[addr] <= #1 di;`
288
289
290			`endif // !VIRTUALSILICON_SSP
291			`endif // !VIRAGE_SSP
292			`endif // !AVANT_ATP
293			`endif // !ARTISAN_SSP
294			`endif // !VENDOR_ALTERA
295			`endif // !VENDOR_XILINX
296			`endif // !VENDOR_FPGA
297
298			`endmodule`
299
300
301			`//`
302			`// Black-box modules`
303			`//`
304
305			`ifdef VENDOR_ALTERA
306			`module altera_ram_sp (`
307			`address,`
308			`inclock,`
309			`we,`
310			`data,`
311			`q) /* synthesis black_box */;`
312
313			`parameter awidth = 7;`
314			`parameter dwidth = 8;`
315
316			`input [awidth -1:0] address;`
317			`input inclock;`
318			`input we;`
319			`input [dwidth -1:0] data;`
320			`output [dwidth -1:0] q;`
321
322			`// synopsis translate_off`
323			`// exemplar translate_off`
324
325			`syn_ram_irou #(`
326			`"UNUSED",`
327			`dwidth,`
328			`awidth,`
329			`1 << awidth`
330			`)`
331			`altera_spram_model (`
332			`.Inclock(inclock),`
333			`.Address(address),`
334			`.Data(data),`
335			`.WE(we),`
336			`.Q(q)`
337			`);`
338
339			`// exemplar translate_on`
340			`// synopsis translate_on`
341
342			`endmodule`
343			`endif // VENDOR_ALTERA
344
345			`ifdef VENDOR_XILINX
346			`module xilinx_ram_sp (`
347			`clk,`
348			`rst,`
349			`addr,`
350			`di,`
351			`en,`
352			`we,`
353			`do) /* synthesis black_box */ ;`
354
355			`parameter awidth = 7;`
356			`parameter dwidth = 8;`
357
358			`input clk;`
359			`input rst;`
360			`input [awidth -1:0] addr;`
361			`input [dwidth -1:0] di;`
362			`input en;`
363			`input we;`
364			`output [dwidth -1:0] do;`
365
366			`// insert simulation model`
367
368
369			`// synopsys translate_off`
370			`// exemplar translate_off`
371
372			`C_MEM_SP_BLOCK_V1_0 #(`
373			`awidth,`
374			`1,`
375			`"0",`
376			`1 << awidth,`
377			`1,`
378			`1,`
379			`1,`
380			`1,`
381			`1,`
382			`1,`
383			`1,`
384			`"",`
385			`16,`
386			`0,`
387			`0,`
388			`1,`
389			`1,`
390			`dwidth`
391			`)`
392			`xilinx_spram_model (`
393			`.CLK(clk),`
394			`.RST(rst),`
395			`.ADDR(addr),`
396			`.DI(di),`
397			`.EN(en),`
398			`.WE(we),`
399			`.DO(do)`
400			`);`
401
402			`// exemplar translate_on`
403			`// synopsys translate_on`
404
405			`endmodule`
406			`endif // VENDOR_XILINX
407