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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant VGA/LCD Core                     ////
////  Enhanced Color Processor                                   ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/vga_lcd ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_colproc.v,v 1.8 2003-05-07 09:48:54 rherveille Exp $
//
//  $Date: 2003-05-07 09:48:54 $
//  $Revision: 1.8 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.7  2002/03/04 11:01:59  rherveille
//               Added 64x64pixels 4bpp hardware cursor support.
//
//               Revision 1.6  2002/02/07 05:42:10  rherveille
//               Fixed some bugs discovered by modified testbench
//               Removed / Changed some strange logic constructions
//               Started work on hardware cursor support (not finished yet)
//               Changed top-level name to vga_enh_top.v
//
 
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
 
module vga_colproc(clk, srst, vdat_buffer_di, ColorDepth, PseudoColor,
        vdat_buffer_empty, vdat_buffer_rreq, rgb_fifo_full,
        rgb_fifo_wreq, r, g, b,
        clut_req, clut_ack, clut_offs, clut_q
        );
 
        //
        // inputs & outputs
        //
        input clk;                    // master clock
        input srst;                   // synchronous reset
 
        input [31:0] vdat_buffer_di;  // video memory data input
 
        input [1:0] ColorDepth;       // color depth (8bpp, 16bpp, 24bpp)
        input       PseudoColor;      // pseudo color enabled (only for 8bpp color depth)
 
        input  vdat_buffer_empty;
        output vdat_buffer_rreq;      // pixel buffer read request
        reg    vdat_buffer_rreq;
 
        input  rgb_fifo_full;
        output rgb_fifo_wreq;
        reg    rgb_fifo_wreq;
        output [7:0] r, g, b;         // pixel color information
        reg    [7:0] r, g, b;
 
        output        clut_req;       // clut request
        reg clut_req;
        input         clut_ack;       // clut acknowledge
        output [ 7:0] clut_offs;      // clut offset
        reg [7:0] clut_offs;
        input  [23:0] clut_q;         // clut data in
 
        //
        // variable declarations
        //
        reg [31:0] DataBuffer;
 
        reg [7:0] Ra, Ga, Ba;
        reg [1:0] colcnt;
        reg RGBbuf_wreq;
 
        //
        // Module body
        //
 
        // store word from pixelbuffer / wishbone input
        always @(posedge clk)
                if (vdat_buffer_rreq)
                        DataBuffer <= #1 vdat_buffer_di;
 
        //
        // generate statemachine
        //
        // extract color information from data buffer
        parameter idle        = 7'b000_0000,
                  fill_buf    = 7'b000_0001,
                  bw_8bpp     = 7'b000_0010,
                  col_8bpp    = 7'b000_0100,
                  col_16bpp_a = 7'b000_1000,
                  col_16bpp_b = 7'b001_0000,
                  col_24bpp   = 7'b010_0000,
                  col_32bpp   = 7'b100_0000;
 
        reg [6:0] c_state;   // synopsys enum_state
        reg [6:0] nxt_state; // synopsys enum_state
 
        // next state decoder
        always @(c_state or vdat_buffer_empty or ColorDepth or PseudoColor or rgb_fifo_full or colcnt or clut_ack)
        begin : nxt_state_decoder
                // initial value
                nxt_state = c_state;
 
                case (c_state) // synopsis full_case parallel_case
                        // idle state
                        idle:
                                if (!vdat_buffer_empty && !rgb_fifo_full)
                                        nxt_state = fill_buf;
 
                        // fill data buffer
                        fill_buf:
                                case (ColorDepth) // synopsis full_case parallel_case
                                        2'b00:
                                                if (PseudoColor)
                                                        nxt_state = col_8bpp;
                                                else
                                                        nxt_state = bw_8bpp;
 
                                        2'b01:
                                                nxt_state = col_16bpp_a;
 
                                        2'b10:
                                                nxt_state = col_24bpp;
 
                                        2'b11:
                                                nxt_state = col_32bpp;
 
                                endcase
 
                        //
                        // 8 bits per pixel
                        //
                        bw_8bpp:
                                if (!rgb_fifo_full && !(|colcnt) )
                                        if (!vdat_buffer_empty)
                                                nxt_state = fill_buf;
                                        else
                                                nxt_state = idle;
 
                        col_8bpp:
                                // Do NOT check for rgb_fifo_full here.
                                // In 8bpp pseudo-color mode the color-processor must always finish
                                // the current 4pixel-block(i.e. it runs until colcnt = '11').
                                // This is because of the late clut-response which shuffles all
                                // signals the state-machine depends on.
                                // Because of this we can not do an early video_memory_data fetch,
                                // i.e. we can not jump to the fill_buf state. Instead we always
                                // jump to idle and check for rgb_fifo_full there.
                                //
                                // The addition of the cursor-processors forces us to increase the
                                // rgb-fifo size. The increased rgb-fifo also handles the above
                                // described problem. Thus erradicating the above comment.
                                // We add the early video_memory_data fetch again.
                                if (!(|colcnt))
                                        if (!vdat_buffer_empty && !rgb_fifo_full)
                                                nxt_state = fill_buf;
                                        else
                                                nxt_state = idle;
 
                        //
                        // 16 bits per pixel
                        //
                        col_16bpp_a:
                                if (!rgb_fifo_full)
                                        nxt_state = col_16bpp_b;
 
                        col_16bpp_b:
                                if (!rgb_fifo_full)
                                        if (!vdat_buffer_empty)
                                                nxt_state = fill_buf;
                                        else
                                                nxt_state = idle;
 
                        //
                        // 24 bits per pixel
                        //
                        col_24bpp:
                                if (!rgb_fifo_full)
                                        if (colcnt == 2'h1) // (colcnt == 1)
                                                nxt_state = col_24bpp; // stay in current state
                                        else if (!vdat_buffer_empty)
                                                nxt_state = fill_buf;
                                        else
                                                nxt_state = idle;
 
                        //
                        // 32 bits per pixel
                        //
                        col_32bpp:
                                if (!rgb_fifo_full)
                                        if (!vdat_buffer_empty)
                                                nxt_state = fill_buf;
                                        else
                                                nxt_state = idle;
                endcase
        end // next state decoder
 
        // generate state registers
        always @(posedge clk)
                        if (srst)
                                c_state <= #1 idle;
                        else
                                c_state <= #1 nxt_state;
 
 
        reg iclut_req;
        reg ivdat_buf_rreq;
        reg [7:0] iR, iG, iB, iRa, iGa, iBa;
 
        // output decoder
        always @(c_state or vdat_buffer_empty or colcnt or DataBuffer or rgb_fifo_full or clut_ack or clut_q or Ba or Ga or Ra)
        begin : output_decoder
 
                // initial values
                ivdat_buf_rreq = 1'b0;
                RGBbuf_wreq = 1'b0;
                iclut_req = 1'b0;
 
                iR  = 'h0;
                iG  = 'h0;
                iB  = 'h0;
                iRa = 'h0;
                iGa = 'h0;
                iBa = 'h0;
 
                case (c_state) // synopsis full_case parallel_case
                        idle:
                                begin
                                        if (!rgb_fifo_full)
                                                if (!vdat_buffer_empty)
                                                        ivdat_buf_rreq = 1'b1;
 
                                        // when entering from 8bpp_pseudo_color_mode
                                        RGBbuf_wreq = clut_ack;
 
                                        iR = clut_q[23:16];
                                        iG = clut_q[15: 8];
                                        iB = clut_q[ 7: 0];
                                end
 
                        fill_buf:
                                begin
                                        // when entering from 8bpp_pseudo_color_mode
                                        RGBbuf_wreq = clut_ack;
 
                                        iR = clut_q[23:16];
                                        iG = clut_q[15: 8];
                                        iB = clut_q[ 7: 0];
                                end
 
                        //              
                        // 8 bits per pixel
                        //
                        bw_8bpp:
                        begin
                                if (!rgb_fifo_full)
                                        begin
                                                RGBbuf_wreq = 1'b1;
 
                                                if ( (!vdat_buffer_empty) && !(|colcnt) )
                                                        ivdat_buf_rreq = 1'b1;
                                        end
 
                                case (colcnt) // synopsis full_case parallel_case
                                        2'b11:
                                        begin
                                                iR = DataBuffer[31:24];
                                                iG = DataBuffer[31:24];
                                                iB = DataBuffer[31:24];
                                        end
 
                                        2'b10:
                                        begin
                                                iR = DataBuffer[23:16];
                                                iG = DataBuffer[23:16];
                                                iB = DataBuffer[23:16];
                                        end
 
                                        2'b01:
                                        begin
                                                iR = DataBuffer[15:8];
                                                iG = DataBuffer[15:8];
                                                iB = DataBuffer[15:8];
                                        end
 
                                        default:
                                        begin
                                                iR = DataBuffer[7:0];
                                                iG = DataBuffer[7:0];
                                                iB = DataBuffer[7:0];
                                        end
                                endcase
                        end
 
                        col_8bpp:
                        begin
                                // Do NOT check for rgb_fifo_full here.
                                // In 8bpp pseudo-color mode the color-processor must always finish
                                // the current 4pixel-block(i.e. it runs until colcnt = '11').
                                // This is because of the late clut-response which shuffles all
                                // signals the state-machine depends on.
                                // Because of this we can not do an early video_memory_data fetch,
                                // i.e. we can not jump to the fill_buf state. Instead we always
                                // jump to idle and check for rgb_fifo_full there.
                                //
                                // The addition of the cursor-processors forces us to increase the
                                // rgb-fifo size. The increased rgb-fifo also handles the above
                                // described problem. Thus erradicating the above comment.
                                // We add the early video_memory_data fetch again.
                                if (!(|colcnt))
                                        if (!vdat_buffer_empty && !rgb_fifo_full)
                                                ivdat_buf_rreq = 1'b1;
 
                                RGBbuf_wreq = clut_ack;
 
                                iR = clut_q[23:16];
                                iG = clut_q[15: 8];
                                iB = clut_q[ 7: 0];
 
                                iclut_req = !rgb_fifo_full || (colcnt[1] ^ colcnt[0]);
                        end
 
                        //
                        // 16 bits per pixel
                        //
                        col_16bpp_a:
                        begin
                                if (!rgb_fifo_full)
                                        RGBbuf_wreq = 1'b1;
 
                                iR[7:3] = DataBuffer[31:27];
                                iG[7:2] = DataBuffer[26:21];
                                iB[7:3] = DataBuffer[20:16];
                        end
 
                        col_16bpp_b:
                        begin
                                if (!rgb_fifo_full)
                                        begin
                                                RGBbuf_wreq = 1'b1;
 
                                                if (!vdat_buffer_empty)
                                                        ivdat_buf_rreq = 1'b1;
                                        end
 
                                iR[7:3] = DataBuffer[15:11];
                                iG[7:2] = DataBuffer[10: 5];
                                iB[7:3] = DataBuffer[ 4: 0];
                        end
 
                        //
                        // 24 bits per pixel
                        //
                        col_24bpp:
                        begin
                                if (!rgb_fifo_full)
                                        begin
                                                RGBbuf_wreq = 1'b1;
 
                                                if ( (colcnt != 2'h1) && !vdat_buffer_empty)
                                                        ivdat_buf_rreq = 1'b1;
                                        end
 
 
                                case (colcnt) // synopsis full_case parallel_case
                                        2'b11:
                                        begin
                                                iR  = DataBuffer[31:24];
                                                iG  = DataBuffer[23:16];
                                                iB  = DataBuffer[15: 8];
                                                iRa = DataBuffer[ 7: 0];
                                        end
 
                                        2'b10:
                                        begin
                                                iR  = Ra;
                                                iG  = DataBuffer[31:24];
                                                iB  = DataBuffer[23:16];
                                                iRa = DataBuffer[15: 8];
                                                iGa = DataBuffer[ 7: 0];
                                        end
 
                                        2'b01:
                                        begin
                                                iR  = Ra;
                                                iG  = Ga;
                                                iB  = DataBuffer[31:24];
                                                iRa = DataBuffer[23:16];
                                                iGa = DataBuffer[15: 8];
                                                iBa = DataBuffer[ 7: 0];
                                        end
 
                                        default:
                                        begin
                                                iR = Ra;
                                                iG = Ga;
                                                iB = Ba;
                                        end
                                endcase
                        end
 
                        //
                        // 32 bits per pixel
                        //
                        col_32bpp:
                        begin
                                if (!rgb_fifo_full)
                                        begin
                                                RGBbuf_wreq = 1'b1;
 
                                                if (!vdat_buffer_empty)
                                                        ivdat_buf_rreq = 1'b1;
                                        end
 
                                iR[7:0] = DataBuffer[23:16];
                                iG[7:0] = DataBuffer[15:8];
                                iB[7:0] = DataBuffer[7:0];
                        end
 
                endcase
        end // output decoder
 
        // generate output registers
        always @(posedge clk)
                begin
                        r  <= #1 iR;
                        g  <= #1 iG;
                        b  <= #1 iB;
 
                        if (RGBbuf_wreq)
                                begin
                                        Ra <= #1 iRa;
                                        Ba <= #1 iBa;
                                        Ga <= #1 iGa;
                                end
 
                        if (srst)
                                begin
                                        vdat_buffer_rreq <= #1 1'b0;
                                        rgb_fifo_wreq <= #1 1'b0;
                                        clut_req <= #1 1'b0;
                                end
                        else
                                begin
                                        vdat_buffer_rreq <= #1 ivdat_buf_rreq;
                                        rgb_fifo_wreq <= #1 RGBbuf_wreq;
                                        clut_req <= #1 iclut_req;
                                end
        end
 
        // assign clut offset
        always @(colcnt or DataBuffer)
          case (colcnt) // synopsis full_case parallel_case
              2'b11: clut_offs = DataBuffer[31:24];
              2'b10: clut_offs = DataBuffer[23:16];
              2'b01: clut_offs = DataBuffer[15: 8];
              2'b00: clut_offs = DataBuffer[ 7: 0];
          endcase
 
 
        //
        // color counter
        //
        always @(posedge clk)
          if (srst)
            colcnt <= #1 2'b11;
          else if (RGBbuf_wreq)
            colcnt <= #1 colcnt -2'h1;
endmodule
 
 

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	30	rherveille	`//// WISHBONE rev.B2 compliant VGA/LCD Core ////`
4			`//// Enhanced Color Processor ////`
5	23	rherveille	`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	30	rherveille	`//// Copyright (C) 2001, 2002 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16	23	rherveille	`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	17	rherveille	`//`
40	53	rherveille	`// $Id: vga_colproc.v,v 1.8 2003-05-07 09:48:54 rherveille Exp $`
41	17	rherveille	`//`
42	53	rherveille	`// $Date: 2003-05-07 09:48:54 $`
43			`// $Revision: 1.8 $`
44	23	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	53	rherveille	`// Revision 1.7 2002/03/04 11:01:59 rherveille`
51			`// Added 64x64pixels 4bpp hardware cursor support.`
52			`//`
53	33	rherveille	`// Revision 1.6 2002/02/07 05:42:10 rherveille`
54			`// Fixed some bugs discovered by modified testbench`
55			`// Removed / Changed some strange logic constructions`
56			`// Started work on hardware cursor support (not finished yet)`
57			`// Changed top-level name to vga_enh_top.v`
58			`//`
59	17	rherveille
60	53	rherveille	`//synopsys translate_off`
61	17	rherveille	`include "timescale.v"
62	53	rherveille	`//synopsys translate_on`
63	17	rherveille
64	30	rherveille	`module vga_colproc(clk, srst, vdat_buffer_di, ColorDepth, PseudoColor,`
65	53	rherveille	`vdat_buffer_empty, vdat_buffer_rreq, rgb_fifo_full,`
66			`rgb_fifo_wreq, r, g, b,`
67			`clut_req, clut_ack, clut_offs, clut_q`
68			`);`
69	17	rherveille
70	19	rherveille	`//`
71	17	rherveille	`// inputs & outputs`
72	19	rherveille	`//`
73	17	rherveille	`input clk; // master clock`
74			`input srst; // synchronous reset`
75
76	33	rherveille	`input [31:0] vdat_buffer_di; // video memory data input`
77	17	rherveille
78			`input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp)`
79	19	rherveille	`input PseudoColor; // pseudo color enabled (only for 8bpp color depth)`
80	17	rherveille
81	30	rherveille	`input vdat_buffer_empty;`
82	33	rherveille	`output vdat_buffer_rreq; // pixel buffer read request`
83	30	rherveille	`reg vdat_buffer_rreq;`
84	17	rherveille
85	30	rherveille	`input rgb_fifo_full;`
86			`output rgb_fifo_wreq;`
87			`reg rgb_fifo_wreq;`
88			`output [7:0] r, g, b; // pixel color information`
89			`reg [7:0] r, g, b;`
90	17	rherveille
91	30	rherveille	`output clut_req; // clut request`
92	19	rherveille	`reg clut_req;`
93	30	rherveille	`input clut_ack; // clut acknowledge`
94			`output [ 7:0] clut_offs; // clut offset`
95	19	rherveille	`reg [7:0] clut_offs;`
96	30	rherveille	`input [23:0] clut_q; // clut data in`
97	19	rherveille
98			`//`
99	17	rherveille	`// variable declarations`
100	19	rherveille	`//`
101	17	rherveille	`reg [31:0] DataBuffer;`
102
103			`reg [7:0] Ra, Ga, Ba;`
104			`reg [1:0] colcnt;`
105			`reg RGBbuf_wreq;`
106
107			`//`
108			`// Module body`
109			`//`
110
111			`// store word from pixelbuffer / wishbone input`
112	53	rherveille	`always @(posedge clk)`
113	30	rherveille	`if (vdat_buffer_rreq)`
114			`DataBuffer <= #1 vdat_buffer_di;`
115	17	rherveille
116			`//`
117			`// generate statemachine`
118			`//`
119			`// extract color information from data buffer`
120	28	rherveille	`parameter idle = 7'b000_0000,`
121			`fill_buf = 7'b000_0001,`
122			`bw_8bpp = 7'b000_0010,`
123			`col_8bpp = 7'b000_0100,`
124			`col_16bpp_a = 7'b000_1000,`
125			`col_16bpp_b = 7'b001_0000,`
126			`col_24bpp = 7'b010_0000,`
127			`col_32bpp = 7'b100_0000;`
128	17	rherveille
129	28	rherveille	`reg [6:0] c_state; // synopsys enum_state`
130			`reg [6:0] nxt_state; // synopsys enum_state`
131	17	rherveille
132			`// next state decoder`
133	53	rherveille	`always @(c_state or vdat_buffer_empty or ColorDepth or PseudoColor or rgb_fifo_full or colcnt or clut_ack)`
134	17	rherveille	`begin : nxt_state_decoder`
135			`// initial value`
136			`nxt_state = c_state;`
137
138			`case (c_state) // synopsis full_case parallel_case`
139			`// idle state`
140			`idle:`
141	30	rherveille	`if (!vdat_buffer_empty && !rgb_fifo_full)`
142	17	rherveille	`nxt_state = fill_buf;`
143
144			`// fill data buffer`
145			`fill_buf:`
146			`case (ColorDepth) // synopsis full_case parallel_case`
147			`2'b00:`
148			`if (PseudoColor)`
149			`nxt_state = col_8bpp;`
150			`else`
151			`nxt_state = bw_8bpp;`
152
153			`2'b01:`
154			`nxt_state = col_16bpp_a;`
155
156	28	rherveille	`2'b10:`
157	17	rherveille	`nxt_state = col_24bpp;`
158
159	28	rherveille	`2'b11:`
160			`nxt_state = col_32bpp;`
161
162	17	rherveille	`endcase`
163
164			`//`
165			`// 8 bits per pixel`
166			`//`
167			`bw_8bpp:`
168	30	rherveille	`if (!rgb_fifo_full && !(\|colcnt) )`
169			`if (!vdat_buffer_empty)`
170	17	rherveille	`nxt_state = fill_buf;`
171			`else`
172			`nxt_state = idle;`
173
174			`col_8bpp:`
175	33	rherveille	`// Do NOT check for rgb_fifo_full here.`
176			`// In 8bpp pseudo-color mode the color-processor must always finish`
177			`// the current 4pixel-block(i.e. it runs until colcnt = '11').`
178	30	rherveille	`// This is because of the late clut-response which shuffles all`
179			`// signals the state-machine depends on.`
180	33	rherveille	`// Because of this we can not do an early video_memory_data fetch,`
181			`// i.e. we can not jump to the fill_buf state. Instead we always`
182			`// jump to idle and check for rgb_fifo_full there.`
183			`//`
184			`// The addition of the cursor-processors forces us to increase the`
185			`// rgb-fifo size. The increased rgb-fifo also handles the above`
186			`// described problem. Thus erradicating the above comment.`
187			`// We add the early video_memory_data fetch again.`
188	30	rherveille	`if (!(\|colcnt))`
189	33	rherveille	`if (!vdat_buffer_empty && !rgb_fifo_full)`
190	30	rherveille	`nxt_state = fill_buf;`
191			`else`
192			`nxt_state = idle;`
193	17	rherveille
194			`//`
195			`// 16 bits per pixel`
196			`//`
197			`col_16bpp_a:`
198	30	rherveille	`if (!rgb_fifo_full)`
199	17	rherveille	`nxt_state = col_16bpp_b;`
200
201			`col_16bpp_b:`
202	30	rherveille	`if (!rgb_fifo_full)`
203			`if (!vdat_buffer_empty)`
204	17	rherveille	`nxt_state = fill_buf;`
205			`else`
206			`nxt_state = idle;`
207
208			`//`
209			`// 24 bits per pixel`
210			`//`
211			`col_24bpp:`
212	30	rherveille	`if (!rgb_fifo_full)`
213	17	rherveille	`if (colcnt == 2'h1) // (colcnt == 1)`
214			`nxt_state = col_24bpp; // stay in current state`
215	30	rherveille	`else if (!vdat_buffer_empty)`
216	17	rherveille	`nxt_state = fill_buf;`
217			`else`
218			`nxt_state = idle;`
219
220	28	rherveille	`//`
221			`// 32 bits per pixel`
222			`//`
223			`col_32bpp:`
224	30	rherveille	`if (!rgb_fifo_full)`
225			`if (!vdat_buffer_empty)`
226	28	rherveille	`nxt_state = fill_buf;`
227			`else`
228			`nxt_state = idle;`
229	17	rherveille	`endcase`
230			`end // next state decoder`
231
232			`// generate state registers`
233	53	rherveille	`always @(posedge clk)`
234	17	rherveille	`if (srst)`
235			`c_state <= #1 idle;`
236			`else`
237			`c_state <= #1 nxt_state;`
238
239
240	19	rherveille	`reg iclut_req;`
241	30	rherveille	`reg ivdat_buf_rreq;`
242	17	rherveille	`reg [7:0] iR, iG, iB, iRa, iGa, iBa;`
243
244			`// output decoder`
245	53	rherveille	`always @(c_state or vdat_buffer_empty or colcnt or DataBuffer or rgb_fifo_full or clut_ack or clut_q or Ba or Ga or Ra)`
246	17	rherveille	`begin : output_decoder`
247
248			`// initial values`
249	30	rherveille	`ivdat_buf_rreq = 1'b0;`
250	17	rherveille	`RGBbuf_wreq = 1'b0;`
251	19	rherveille	`iclut_req = 1'b0;`
252	17	rherveille
253			`iR = 'h0;`
254			`iG = 'h0;`
255			`iB = 'h0;`
256			`iRa = 'h0;`
257			`iGa = 'h0;`
258			`iBa = 'h0;`
259
260			`case (c_state) // synopsis full_case parallel_case`
261			`idle:`
262	30	rherveille	`begin`
263			`if (!rgb_fifo_full)`
264			`if (!vdat_buffer_empty)`
265			`ivdat_buf_rreq = 1'b1;`
266	17	rherveille
267	30	rherveille	`// when entering from 8bpp_pseudo_color_mode`
268			`RGBbuf_wreq = clut_ack;`
269
270			`iR = clut_q[23:16];`
271			`iG = clut_q[15: 8];`
272			`iB = clut_q[ 7: 0];`
273			`end`
274
275			`fill_buf:`
276			`begin`
277			`// when entering from 8bpp_pseudo_color_mode`
278			`RGBbuf_wreq = clut_ack;`
279
280			`iR = clut_q[23:16];`
281			`iG = clut_q[15: 8];`
282			`iB = clut_q[ 7: 0];`
283			`end`
284
285	17	rherveille	`//`
286			`// 8 bits per pixel`
287			`//`
288			`bw_8bpp:`
289			`begin`
290	30	rherveille	`if (!rgb_fifo_full)`
291	17	rherveille	`begin`
292			`RGBbuf_wreq = 1'b1;`
293
294	30	rherveille	`if ( (!vdat_buffer_empty) && !(\|colcnt) )`
295			`ivdat_buf_rreq = 1'b1;`
296	17	rherveille	`end`
297
298			`case (colcnt) // synopsis full_case parallel_case`
299			`2'b11:`
300			`begin`
301			`iR = DataBuffer[31:24];`
302			`iG = DataBuffer[31:24];`
303			`iB = DataBuffer[31:24];`
304			`end`
305
306			`2'b10:`
307			`begin`
308			`iR = DataBuffer[23:16];`
309			`iG = DataBuffer[23:16];`
310			`iB = DataBuffer[23:16];`
311			`end`
312
313			`2'b01:`
314			`begin`
315			`iR = DataBuffer[15:8];`
316			`iG = DataBuffer[15:8];`
317			`iB = DataBuffer[15:8];`
318			`end`
319
320			`default:`
321			`begin`
322			`iR = DataBuffer[7:0];`
323			`iG = DataBuffer[7:0];`
324			`iB = DataBuffer[7:0];`
325			`end`
326			`endcase`
327			`end`
328
329			`col_8bpp:`
330			`begin`
331	33	rherveille	`// Do NOT check for rgb_fifo_full here.`
332			`// In 8bpp pseudo-color mode the color-processor must always finish`
333			`// the current 4pixel-block(i.e. it runs until colcnt = '11').`
334	30	rherveille	`// This is because of the late clut-response which shuffles all`
335			`// signals the state-machine depends on.`
336	33	rherveille	`// Because of this we can not do an early video_memory_data fetch,`
337			`// i.e. we can not jump to the fill_buf state. Instead we always`
338			`// jump to idle and check for rgb_fifo_full there.`
339			`//`
340			`// The addition of the cursor-processors forces us to increase the`
341			`// rgb-fifo size. The increased rgb-fifo also handles the above`
342			`// described problem. Thus erradicating the above comment.`
343			`// We add the early video_memory_data fetch again.`
344	30	rherveille	`if (!(\|colcnt))`
345	33	rherveille	`if (!vdat_buffer_empty && !rgb_fifo_full)`
346	30	rherveille	`ivdat_buf_rreq = 1'b1;`
347	17	rherveille
348	30	rherveille	`RGBbuf_wreq = clut_ack;`
349	17	rherveille
350	19	rherveille	`iR = clut_q[23:16];`
351			`iG = clut_q[15: 8];`
352			`iB = clut_q[ 7: 0];`
353	17	rherveille
354	30	rherveille	`iclut_req = !rgb_fifo_full \|\| (colcnt[1] ^ colcnt[0]);`
355	17	rherveille	`end`
356
357			`//`
358			`// 16 bits per pixel`
359			`//`
360			`col_16bpp_a:`
361			`begin`
362	30	rherveille	`if (!rgb_fifo_full)`
363	17	rherveille	`RGBbuf_wreq = 1'b1;`
364
365			`iR[7:3] = DataBuffer[31:27];`
366			`iG[7:2] = DataBuffer[26:21];`
367			`iB[7:3] = DataBuffer[20:16];`
368			`end`
369
370			`col_16bpp_b:`
371			`begin`
372	30	rherveille	`if (!rgb_fifo_full)`
373	17	rherveille	`begin`
374			`RGBbuf_wreq = 1'b1;`
375
376	30	rherveille	`if (!vdat_buffer_empty)`
377			`ivdat_buf_rreq = 1'b1;`
378	17	rherveille	`end`
379
380			`iR[7:3] = DataBuffer[15:11];`
381			`iG[7:2] = DataBuffer[10: 5];`
382			`iB[7:3] = DataBuffer[ 4: 0];`
383			`end`
384
385			`//`
386			`// 24 bits per pixel`
387			`//`
388			`col_24bpp:`
389			`begin`
390	30	rherveille	`if (!rgb_fifo_full)`
391	17	rherveille	`begin`
392			`RGBbuf_wreq = 1'b1;`
393
394	30	rherveille	`if ( (colcnt != 2'h1) && !vdat_buffer_empty)`
395			`ivdat_buf_rreq = 1'b1;`
396	17	rherveille	`end`
397
398
399			`case (colcnt) // synopsis full_case parallel_case`
400			`2'b11:`
401			`begin`
402			`iR = DataBuffer[31:24];`
403			`iG = DataBuffer[23:16];`
404			`iB = DataBuffer[15: 8];`
405			`iRa = DataBuffer[ 7: 0];`
406			`end`
407
408			`2'b10:`
409			`begin`
410			`iR = Ra;`
411			`iG = DataBuffer[31:24];`
412			`iB = DataBuffer[23:16];`
413			`iRa = DataBuffer[15: 8];`
414			`iGa = DataBuffer[ 7: 0];`
415			`end`
416
417			`2'b01:`
418			`begin`
419			`iR = Ra;`
420			`iG = Ga;`
421			`iB = DataBuffer[31:24];`
422			`iRa = DataBuffer[23:16];`
423			`iGa = DataBuffer[15: 8];`
424			`iBa = DataBuffer[ 7: 0];`
425			`end`
426
427			`default:`
428			`begin`
429			`iR = Ra;`
430			`iG = Ga;`
431			`iB = Ba;`
432			`end`
433			`endcase`
434			`end`
435
436	28	rherveille	`//`
437			`// 32 bits per pixel`
438			`//`
439			`col_32bpp:`
440			`begin`
441	30	rherveille	`if (!rgb_fifo_full)`
442	28	rherveille	`begin`
443			`RGBbuf_wreq = 1'b1;`
444
445	30	rherveille	`if (!vdat_buffer_empty)`
446			`ivdat_buf_rreq = 1'b1;`
447	28	rherveille	`end`
448
449			`iR[7:0] = DataBuffer[23:16];`
450			`iG[7:0] = DataBuffer[15:8];`
451			`iB[7:0] = DataBuffer[7:0];`
452			`end`
453
454	17	rherveille	`endcase`
455			`end // output decoder`
456
457			`// generate output registers`
458	53	rherveille	`always @(posedge clk)`
459	17	rherveille	`begin`
460	30	rherveille	`r <= #1 iR;`
461			`g <= #1 iG;`
462			`b <= #1 iB;`
463	17	rherveille
464			`if (RGBbuf_wreq)`
465			`begin`
466			`Ra <= #1 iRa;`
467			`Ba <= #1 iBa;`
468			`Ga <= #1 iGa;`
469			`end`
470
471			`if (srst)`
472			`begin`
473	30	rherveille	`vdat_buffer_rreq <= #1 1'b0;`
474			`rgb_fifo_wreq <= #1 1'b0;`
475	17	rherveille	`clut_req <= #1 1'b0;`
476			`end`
477			`else`
478			`begin`
479	30	rherveille	`vdat_buffer_rreq <= #1 ivdat_buf_rreq;`
480			`rgb_fifo_wreq <= #1 RGBbuf_wreq;`
481	19	rherveille	`clut_req <= #1 iclut_req;`
482	17	rherveille	`end`
483			`end`
484
485			`// assign clut offset`
486	53	rherveille	`always @(colcnt or DataBuffer)`
487			`case (colcnt) // synopsis full_case parallel_case`
488			`2'b11: clut_offs = DataBuffer[31:24];`
489			`2'b10: clut_offs = DataBuffer[23:16];`
490			`2'b01: clut_offs = DataBuffer[15: 8];`
491			`2'b00: clut_offs = DataBuffer[ 7: 0];`
492			`endcase`
493	17	rherveille
494
495			`//`
496			`// color counter`
497			`//`
498	53	rherveille	`always @(posedge clk)`
499			`if (srst)`
500			`colcnt <= #1 2'b11;`

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