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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo.v] - Blame information for rev 17

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//
// File fifo.v (universal FIFO)
// Author : Richard Herveille
// rev.: 1.0 August  7th, 2001. Initial Verilog release
// rev.: 1.1 August 29th, 2001. Created asynchronous 'q' output. Try to get the core up to speed.
 
`include "timescale.v"
 
module vga_fifo (clk, aclr, sclr, d, wreq, q, rreq, empty, hfull, full);
 
        //
        // parameters
        //
 
        parameter AWIDTH = 7;  // 128 entries
        parameter DWIDTH = 32; // 32bits data
 
        //
        // inputs & outputs
        //
 
        input clk; // clock input
        input aclr; // active low asynchronous clear
        input sclr; // active high synchronous clear
 
        input [DWIDTH -1:0] d; // data input
        input wreq;            // write request
 
        output [DWIDTH -1:0] q; // data output
//      reg [DWIDTH -1:0] q;
        input  rreq;            // read request
 
        output empty;           // fifo is empty
        output hfull;           // fifo is half full
        output full;            // fifo is full
 
 
        //
        // variable declarations
        //
        parameter DEPTH = 1 << AWIDTH;
 
        reg [DWIDTH -1:0] mem [DEPTH -1:0];
 
        reg [AWIDTH -1:0] rptr, wptr;
        reg [AWIDTH   :0] fifo_cnt;
 
        //
        // Module body
        //
 
        // read pointer
        always@(posedge clk or negedge aclr)
                if (!aclr)
                        rptr <= #1 0;
                else if (sclr)
                        rptr <= #1 0;
                else if (rreq)
                        rptr <= #1 rptr + 1;
 
        // write pointer
        always@(posedge clk or negedge aclr)
                if (!aclr)
                        wptr <= #1 0;
                else if (sclr)
                        wptr <= #1 0;
                else if (wreq)
                        wptr <= #1 wptr + 1;
 
        // memory array operations
        /*
        always@(posedge clk)
                begin
                        if (wreq)
                                mem[wptr] <= #1 d;
 
                        q <= #1 mem[rptr];
 
                end
        */
        always@(posedge clk)
                if (wreq)
                        mem[wptr] <= #1 d;
 
        assign q = mem[rptr];
 
        // number of words in fifo
        always@(posedge clk or negedge aclr)
                if (!aclr)
                        fifo_cnt <= #1 0;
                else if (sclr)
                        fifo_cnt <= #1 0;
                else
                        begin
                                if (wreq & !rreq)
                                        fifo_cnt <= #1 fifo_cnt + 1;
                                else if (rreq & !wreq)
                                        fifo_cnt <= #1 fifo_cnt - 1;
                        end
 
        // status flags
        assign empty = !(|fifo_cnt);
        assign hfull = fifo_cnt[AWIDTH -1];
        assign full  = fifo_cnt[AWIDTH];
endmodule
 
 

Line No.	Rev	Author	Line
1	17	rherveille	`//`
2			`// File fifo.v (universal FIFO)`
3			`// Author : Richard Herveille`
4			`// rev.: 1.0 August 7th, 2001. Initial Verilog release`
5			`// rev.: 1.1 August 29th, 2001. Created asynchronous 'q' output. Try to get the core up to speed.`
6
7			`include "timescale.v"
8
9			`module vga_fifo (clk, aclr, sclr, d, wreq, q, rreq, empty, hfull, full);`
10
11			`//`
12			`// parameters`
13			`//`
14
15			`parameter AWIDTH = 7; // 128 entries`
16			`parameter DWIDTH = 32; // 32bits data`
17
18			`//`
19			`// inputs & outputs`
20			`//`
21
22			`input clk; // clock input`
23			`input aclr; // active low asynchronous clear`
24			`input sclr; // active high synchronous clear`
25
26			`input [DWIDTH -1:0] d; // data input`
27			`input wreq; // write request`
28
29			`output [DWIDTH -1:0] q; // data output`
30			`// reg [DWIDTH -1:0] q;`
31			`input rreq; // read request`
32
33			`output empty; // fifo is empty`
34			`output hfull; // fifo is half full`
35			`output full; // fifo is full`
36
37
38			`//`
39			`// variable declarations`
40			`//`
41			`parameter DEPTH = 1 << AWIDTH;`
42
43			`reg [DWIDTH -1:0] mem [DEPTH -1:0];`
44
45			`reg [AWIDTH -1:0] rptr, wptr;`
46			`reg [AWIDTH :0] fifo_cnt;`
47
48			`//`
49			`// Module body`
50			`//`
51
52			`// read pointer`
53			`always@(posedge clk or negedge aclr)`
54			`if (!aclr)`
55			`rptr <= #1 0;`
56			`else if (sclr)`
57			`rptr <= #1 0;`
58			`else if (rreq)`
59			`rptr <= #1 rptr + 1;`
60
61			`// write pointer`
62			`always@(posedge clk or negedge aclr)`
63			`if (!aclr)`
64			`wptr <= #1 0;`
65			`else if (sclr)`
66			`wptr <= #1 0;`
67			`else if (wreq)`
68			`wptr <= #1 wptr + 1;`
69
70			`// memory array operations`
71			`/*`
72			`always@(posedge clk)`
73			`begin`
74			`if (wreq)`
75			`mem[wptr] <= #1 d;`
76
77			`q <= #1 mem[rptr];`
78
79			`end`
80			`*/`
81			`always@(posedge clk)`
82			`if (wreq)`
83			`mem[wptr] <= #1 d;`
84
85			`assign q = mem[rptr];`
86
87			`// number of words in fifo`
88			`always@(posedge clk or negedge aclr)`
89			`if (!aclr)`
90			`fifo_cnt <= #1 0;`
91			`else if (sclr)`
92			`fifo_cnt <= #1 0;`
93			`else`
94			`begin`
95			`if (wreq & !rreq)`
96			`fifo_cnt <= #1 fifo_cnt + 1;`
97			`else if (rreq & !wreq)`
98			`fifo_cnt <= #1 fifo_cnt - 1;`
99			`end`
100
101			`// status flags`
102			`assign empty = !(\|fifo_cnt);`
103			`assign hfull = fifo_cnt[AWIDTH -1];`
104			`assign full = fifo_cnt[AWIDTH];`
105			`endmodule`
106
107

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo.v] - Blame information for rev 17