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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo.v] - Blame information for rev 28

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant VGA/LCD Core; Universal Fifo     ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/vga_lcd ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_fifo.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
//
//  $Date: 2002-01-28 03:47:16 $
//  $Revision: 1.5 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
 
`include "timescale.v"
 
module vga_fifo (clk, aclr, sclr, d, wreq, q, rreq, empty, hfull, full);
 
        //
        // parameters
        //
 
        parameter AWIDTH = 7;  // 128 entries
        parameter DWIDTH = 32; // 32bits data
 
        //
        // inputs & outputs
        //
 
        input clk; // clock input
        input aclr; // active low asynchronous clear
        input sclr; // active high synchronous clear
 
        input [DWIDTH -1:0] d; // data input
        input wreq;            // write request
 
        output [DWIDTH -1:0] q; // data output
//      reg [DWIDTH -1:0] q;
        input  rreq;            // read request
 
        output empty;           // fifo is empty
        output hfull;           // fifo is half full
        output full;            // fifo is full
 
 
        //
        // variable declarations
        //
        parameter DEPTH = 1 << AWIDTH;
 
        reg [DWIDTH -1:0] mem [DEPTH -1:0];
 
        reg [AWIDTH -1:0] rptr, wptr;
        reg [AWIDTH   :0] fifo_cnt;
 
        //
        // Module body
        //
 
        // read pointer
        always@(posedge clk or negedge aclr)
                if (!aclr)
                        rptr <= #1 0;
                else if (sclr)
                        rptr <= #1 0;
                else if (rreq)
                        rptr <= #1 rptr + 1;
 
        // write pointer
        always@(posedge clk or negedge aclr)
                if (!aclr)
                        wptr <= #1 0;
                else if (sclr)
                        wptr <= #1 0;
                else if (wreq)
                        wptr <= #1 wptr + 1;
 
        // memory array operations
        always@(posedge clk)
                if (wreq)
                        mem[wptr] <= #1 d;
 
        assign q = mem[rptr];
 
        // number of words in fifo
        always@(posedge clk or negedge aclr)
                if (!aclr)
                        fifo_cnt <= #1 0;
                else if (sclr)
                        fifo_cnt <= #1 0;
                else
                        begin
                                if (wreq & !rreq)
                                        fifo_cnt <= #1 fifo_cnt + 1;
                                else if (rreq & !wreq)
                                        fifo_cnt <= #1 fifo_cnt - 1;
                        end
 
        // status flags
        assign empty = !(|fifo_cnt);
        assign hfull = fifo_cnt[AWIDTH -1];
        assign full  = fifo_cnt[AWIDTH];
endmodule

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant VGA/LCD Core; Universal Fifo ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	17	rherveille	`//`
40	28	rherveille	`// $Id: vga_fifo.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $`
41	23	rherveille	`//`
42	28	rherveille	`// $Date: 2002-01-28 03:47:16 $`
43			`// $Revision: 1.5 $`
44	23	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	17	rherveille
51			`include "timescale.v"
52
53			`module vga_fifo (clk, aclr, sclr, d, wreq, q, rreq, empty, hfull, full);`
54
55			`//`
56			`// parameters`
57			`//`
58
59			`parameter AWIDTH = 7; // 128 entries`
60			`parameter DWIDTH = 32; // 32bits data`
61
62			`//`
63			`// inputs & outputs`
64			`//`
65
66			`input clk; // clock input`
67			`input aclr; // active low asynchronous clear`
68			`input sclr; // active high synchronous clear`
69
70			`input [DWIDTH -1:0] d; // data input`
71			`input wreq; // write request`
72
73			`output [DWIDTH -1:0] q; // data output`
74			`// reg [DWIDTH -1:0] q;`
75			`input rreq; // read request`
76
77			`output empty; // fifo is empty`
78			`output hfull; // fifo is half full`
79			`output full; // fifo is full`
80
81
82			`//`
83			`// variable declarations`
84			`//`
85			`parameter DEPTH = 1 << AWIDTH;`
86
87			`reg [DWIDTH -1:0] mem [DEPTH -1:0];`
88
89			`reg [AWIDTH -1:0] rptr, wptr;`
90			`reg [AWIDTH :0] fifo_cnt;`
91
92			`//`
93			`// Module body`
94			`//`
95
96			`// read pointer`
97			`always@(posedge clk or negedge aclr)`
98			`if (!aclr)`
99			`rptr <= #1 0;`
100			`else if (sclr)`
101			`rptr <= #1 0;`
102			`else if (rreq)`
103			`rptr <= #1 rptr + 1;`
104
105			`// write pointer`
106			`always@(posedge clk or negedge aclr)`
107			`if (!aclr)`
108			`wptr <= #1 0;`
109			`else if (sclr)`
110			`wptr <= #1 0;`
111			`else if (wreq)`
112			`wptr <= #1 wptr + 1;`
113
114			`// memory array operations`
115			`always@(posedge clk)`
116			`if (wreq)`
117			`mem[wptr] <= #1 d;`
118
119			`assign q = mem[rptr];`
120
121			`// number of words in fifo`
122			`always@(posedge clk or negedge aclr)`
123			`if (!aclr)`
124			`fifo_cnt <= #1 0;`
125			`else if (sclr)`
126			`fifo_cnt <= #1 0;`
127			`else`
128			`begin`
129			`if (wreq & !rreq)`
130			`fifo_cnt <= #1 fifo_cnt + 1;`
131			`else if (rreq & !wreq)`
132			`fifo_cnt <= #1 fifo_cnt - 1;`
133			`end`
134
135			`// status flags`
136			`assign empty = !(\|fifo_cnt);`
137			`assign hfull = fifo_cnt[AWIDTH -1];`
138			`assign full = fifo_cnt[AWIDTH];`
139			`endmodule`

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo.v] - Blame information for rev 28