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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  generic FIFO, uses LFSRs for read/write pointers           ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_fifo.v,v 1.7 2003-05-07 09:48:54 rherveille Exp $
//
//  $Date: 2003-05-07 09:48:54 $
//  $Revision: 1.7 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.6  2002/02/07 05:42:10  rherveille
//               Fixed some bugs discovered by modified testbench
//               Removed / Changed some strange logic constructions
//               Started work on hardware cursor support (not finished yet)
//               Changed top-level name to vga_enh_top.v
//
 
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
 
 
// set FIFO_RW_CHECK to prevent writing to a full and reading from an empty FIFO
//`define FIFO_RW_CHECK
 
// Long Pseudo Random Generators can generate (N^2 -1) combinations. This means
// 1 FIFO entry is unavailable. This might be a problem, especially for small
// FIFOs. Setting VGA_FIFO_ALL_ENTRIES creates additional logic that ensures that
// all FIFO entries are used at the expense of some additional logic.
`define VGA_FIFO_ALL_ENTRIES
 
module vga_fifo (
        clk,
        aclr,
        sclr,
        wreq,
        rreq,
        d,
        q,
        nword,
        empty,
        full,
        aempty,
        afull
        );
 
        //
        // parameters
        //
        parameter aw =  3;                         // no.of entries (in bits; 2^7=128 entries)
        parameter dw =  8;                         // datawidth (in bits)
 
        //
        // inputs & outputs
        //
        input             clk;                     // master clock
        input             aclr;                    // asynchronous active low reset
        input             sclr;                    // synchronous active high reset
 
        input             wreq;                    // write request
        input             rreq;                    // read request
        input  [dw:1]     d;                       // data-input
        output [dw:1]     q;                       // data-output
 
        output [aw:1]     nword;                   // number of words in FIFO
 
        output            empty;                   // fifo empty
        output            full;                    // fifo full
 
        output            aempty;                  // fifo asynchronous/almost empty (1 entry left)
        output            afull;                   // fifo asynchronous/almost full (1 entry left)
 
        reg [aw:1] nword;
        reg        empty, full;
 
        //
        // Module body
        //
        reg  [aw:1] rp, wp;
        wire [dw:1] ramq;
        wire fwreq, frreq;
 
`ifdef VGA_FIFO_ALL_ENTRIES
        function lsb;
           input [aw:1] q;
           case (aw)
               2: lsb = ~q[2];
               3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
               4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
               5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
               6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
               7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
               8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
               9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
              10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
              11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
              12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
              13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
              14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
              15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
              16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
           endcase
        endfunction
`else
        function lsb;
           input [aw:1] q;
           case (aw)
               2: lsb = ~q[2];
               3: lsb = ~(q[3] ^ q[2]);
               4: lsb = ~(q[4] ^ q[3]);
               5: lsb = ~(q[5] ^ q[3]);
               6: lsb = ~(q[6] ^ q[5]);
               7: lsb = ~(q[7] ^ q[6]);
               8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
               9: lsb = ~(q[9] ^ q[5]);
              10: lsb = ~(q[10] ^ q[7]);
              11: lsb = ~(q[11] ^ q[9]);
              12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
              13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
              14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
              15: lsb = ~(q[15] ^ q[14]);
              16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
           endcase
        endfunction
`endif
 
`ifdef RW_CHECK
  assign fwreq = wreq & ~full;
  assign frreq = rreq & ~empty;
`else
  assign fwreq = wreq;
  assign frreq = rreq;
`endif
 
        //
        // hookup read-pointer
        //
        always @(posedge clk or negedge aclr)
          if (~aclr)      rp <= #1 0;
          else if (sclr)  rp <= #1 0;
          else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};
 
        //
        // hookup write-pointer
        //
        always @(posedge clk or negedge aclr)
          if (~aclr)      wp <= #1 0;
          else if (sclr)  wp <= #1 0;
          else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};
 
 
        //
        // hookup memory-block
        //
        reg [dw:1] mem [(1<<aw) -1:0];
 
        // memory array operations
        always @(posedge clk)
          if (fwreq)
            mem[wp] <= #1 d;
 
        assign q = mem[rp];
 
 
        // generate full/empty signals
        assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;
        always @(posedge clk or negedge aclr)
          if (~aclr)
            empty <= #1 1'b1;
          else if (sclr)
            empty <= #1 1'b1;
          else
            empty <= #1 aempty | (empty & (~fwreq + frreq));
 
        assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;
        always @(posedge clk or negedge aclr)
          if (~aclr)
            full <= #1 1'b0;
          else if (sclr)
            full <= #1 1'b0;
          else
            full <= #1 afull | ( full & (~frreq + fwreq) );
 
        // number of words in fifo
        always @(posedge clk or negedge aclr)
          if (~aclr)
            nword <= #1 0;
          else if (sclr)
            nword <= #1 0;
          else
            begin
                if (wreq & !rreq)
                  nword <= #1 nword +1;
                else if (rreq & !wreq)
                  nword <= #1 nword -1;
            end
 
        //
        // Simulation checks
        //
        // synopsys translate_off
        always @(posedge clk)
          if (full & fwreq)
            $display("Writing while FIFO full\n");
 
        always @(posedge clk)
          if (empty & frreq)
            $display("Reading while FIFO empty\n");
        // synopsys translate_on
endmodule
 
 

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	53	rherveille	`//// generic FIFO, uses LFSRs for read/write pointers ////`
4	23	rherveille	`//// ////`
5			`//// Author: Richard Herveille ////`
6			`//// richard@asics.ws ////`
7			`//// www.asics.ws ////`
8			`//// ////`
9			`/////////////////////////////////////////////////////////////////////`
10			`//// ////`
11	53	rherveille	`//// Copyright (C) 2001, 2002 Richard Herveille ////`
12			`//// richard@asics.ws ////`
13	23	rherveille	`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer.////`
18			`//// ////`
19			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
20			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
21			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
22			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
23			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
24			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
25			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
26			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
27			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
28			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
29			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
30			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
31			`//// POSSIBILITY OF SUCH DAMAGE. ////`
32			`//// ////`
33			`/////////////////////////////////////////////////////////////////////`
34
35			`// CVS Log`
36	17	rherveille	`//`
37	53	rherveille	`// $Id: vga_fifo.v,v 1.7 2003-05-07 09:48:54 rherveille Exp $`
38	23	rherveille	`//`
39	53	rherveille	`// $Date: 2003-05-07 09:48:54 $`
40			`// $Revision: 1.7 $`
41	23	rherveille	`// $Author: rherveille $`
42			`// $Locker: $`
43			`// $State: Exp $`
44			`//`
45			`// Change History:`
46			`// $Log: not supported by cvs2svn $`
47	53	rherveille	`// Revision 1.6 2002/02/07 05:42:10 rherveille`
48			`// Fixed some bugs discovered by modified testbench`
49			`// Removed / Changed some strange logic constructions`
50			`// Started work on hardware cursor support (not finished yet)`
51			`// Changed top-level name to vga_enh_top.v`
52			`//`
53	17	rherveille
54	53	rherveille	`//synopsys translate_off`
55	17	rherveille	`include "timescale.v"
56	53	rherveille	`//synopsys translate_on`
57	17	rherveille
58
59	53	rherveille	`// set FIFO_RW_CHECK to prevent writing to a full and reading from an empty FIFO`
60			//`define FIFO_RW_CHECK
61
62			`// Long Pseudo Random Generators can generate (N^2 -1) combinations. This means`
63			`// 1 FIFO entry is unavailable. This might be a problem, especially for small`
64			`// FIFOs. Setting VGA_FIFO_ALL_ENTRIES creates additional logic that ensures that`
65			`// all FIFO entries are used at the expense of some additional logic.`
66			`define VGA_FIFO_ALL_ENTRIES
67
68			`module vga_fifo (`
69			`clk,`
70			`aclr,`
71			`sclr,`
72			`wreq,`
73			`rreq,`
74			`d,`
75			`q,`
76			`nword,`
77			`empty,`
78			`full,`
79			`aempty,`
80			`afull`
81			`);`
82
83	17	rherveille	`//`
84			`// parameters`
85			`//`
86	53	rherveille	`parameter aw = 3; // no.of entries (in bits; 2^7=128 entries)`
87			`parameter dw = 8; // datawidth (in bits)`
88	17	rherveille
89			`//`
90			`// inputs & outputs`
91			`//`
92	53	rherveille	`input clk; // master clock`
93			`input aclr; // asynchronous active low reset`
94			`input sclr; // synchronous active high reset`
95	17	rherveille
96	53	rherveille	`input wreq; // write request`
97			`input rreq; // read request`
98			`input [dw:1] d; // data-input`
99			`output [dw:1] q; // data-output`
100	17	rherveille
101	53	rherveille	`output [aw:1] nword; // number of words in FIFO`
102	17	rherveille
103	53	rherveille	`output empty; // fifo empty`
104			`output full; // fifo full`
105	17	rherveille
106	53	rherveille	`output aempty; // fifo asynchronous/almost empty (1 entry left)`
107			`output afull; // fifo asynchronous/almost full (1 entry left)`
108	17	rherveille
109	53	rherveille	`reg [aw:1] nword;`
110			`reg empty, full;`
111
112	17	rherveille	`//`
113	53	rherveille	`// Module body`
114	17	rherveille	`//`
115	53	rherveille	`reg [aw:1] rp, wp;`
116			`wire [dw:1] ramq;`
117			`wire fwreq, frreq;`
118	17	rherveille
119	53	rherveille	`ifdef VGA_FIFO_ALL_ENTRIES
120			`function lsb;`
121			`input [aw:1] q;`
122			`case (aw)`
123			`2: lsb = ~q[2];`
124			`3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);`
125			`4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);`
126			`5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);`
127			`6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);`
128			`7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);`
129			`8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);`
130			`9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);`
131			`10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);`
132			`11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);`
133			`12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);`
134			`13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);`
135			`14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);`
136			`15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);`
137			`16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);`
138			`endcase`
139			`endfunction`
140			`else
141			`function lsb;`
142			`input [aw:1] q;`
143			`case (aw)`
144			`2: lsb = ~q[2];`
145			`3: lsb = ~(q[3] ^ q[2]);`
146			`4: lsb = ~(q[4] ^ q[3]);`
147			`5: lsb = ~(q[5] ^ q[3]);`
148			`6: lsb = ~(q[6] ^ q[5]);`
149			`7: lsb = ~(q[7] ^ q[6]);`
150			`8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);`
151			`9: lsb = ~(q[9] ^ q[5]);`
152			`10: lsb = ~(q[10] ^ q[7]);`
153			`11: lsb = ~(q[11] ^ q[9]);`
154			`12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);`
155			`13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);`
156			`14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);`
157			`15: lsb = ~(q[15] ^ q[14]);`
158			`16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);`
159			`endcase`
160			`endfunction`
161			`endif
162	17	rherveille
163	53	rherveille	`ifdef RW_CHECK
164			`assign fwreq = wreq & ~full;`
165			`assign frreq = rreq & ~empty;`
166			`else
167			`assign fwreq = wreq;`
168			`assign frreq = rreq;`
169			`endif
170	17	rherveille
171			`//`
172	53	rherveille	`// hookup read-pointer`
173	17	rherveille	`//`
174	53	rherveille	`always @(posedge clk or negedge aclr)`
175			`if (~aclr) rp <= #1 0;`
176			`else if (sclr) rp <= #1 0;`
177			`else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};`
178	17	rherveille
179	53	rherveille	`//`
180			`// hookup write-pointer`
181			`//`
182			`always @(posedge clk or negedge aclr)`
183			`if (~aclr) wp <= #1 0;`
184			`else if (sclr) wp <= #1 0;`
185			`else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};`
186	17	rherveille
187
188	53	rherveille	`//`
189			`// hookup memory-block`
190			`//`
191			`reg [dw:1] mem [(1<<aw) -1:0];`
192
193	17	rherveille	`// memory array operations`
194	53	rherveille	`always @(posedge clk)`
195			`if (fwreq)`
196			`mem[wp] <= #1 d;`
197	17	rherveille
198	53	rherveille	`assign q = mem[rp];`
199
200
201			`// generate full/empty signals`
202			`assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;`
203			`always @(posedge clk or negedge aclr)`
204			`if (~aclr)`
205			`empty <= #1 1'b1;`
206			`else if (sclr)`
207			`empty <= #1 1'b1;`
208			`else`
209			`empty <= #1 aempty \| (empty & (~fwreq + frreq));`
210
211			`assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;`
212			`always @(posedge clk or negedge aclr)`
213			`if (~aclr)`
214			`full <= #1 1'b0;`
215			`else if (sclr)`
216			`full <= #1 1'b0;`
217			`else`
218			`full <= #1 afull \| ( full & (~frreq + fwreq) );`
219
220	17	rherveille	`// number of words in fifo`
221	53	rherveille	`always @(posedge clk or negedge aclr)`
222			`if (~aclr)`
223			`nword <= #1 0;`
224			`else if (sclr)`
225			`nword <= #1 0;`
226			`else`
227			`begin`
228			`if (wreq & !rreq)`
229			`nword <= #1 nword +1;`
230			`else if (rreq & !wreq)`
231			`nword <= #1 nword -1;`
232			`end`
233	17	rherveille
234	53	rherveille	`//`
235			`// Simulation checks`
236			`//`
237			`// synopsys translate_off`
238			`always @(posedge clk)`
239			`if (full & fwreq)`
240			`$display("Writing while FIFO full\n");`
241
242			`always @(posedge clk)`
243			`if (empty & frreq)`
244			`$display("Reading while FIFO empty\n");`
245			`// synopsys translate_on`
246	17	rherveille	`endmodule`
247	30	rherveille
248	53	rherveille

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo.v] - Blame information for rev 53