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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo_dc.v] - Blame information for rev 62

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant VGA/LCD Core; Dual Clocked Fifo  ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/vga_lcd ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_fifo_dc.v,v 1.6 2003-08-01 11:46:38 rherveille Exp $
//
//  $Date: 2003-08-01 11:46:38 $
//  $Revision: 1.6 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.5  2003/05/07 09:48:54  rherveille
//               Fixed some Wishbone RevB.3 related bugs.
//               Changed layout of the core. Blocks are located more logically now.
//               Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
//
//               Revision 1.4  2002/01/28 03:47:16  rherveille
//               Changed counter-library.
//               Changed vga-core.
//               Added 32bpp mode.
//
 
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
 
 
/*
 
  Dual clock FIFO.
 
  Uses gray codes to move from one clock domain to the other.
 
  Flags are synchronous to the related clock domain;
  - empty: synchronous to read_clock
  - full : synchronous to write_clock
 
  CLR is available in both clock-domains.
  Asserting any clr signal resets the entire FIFO.
  When crossing clock domains the clears are synchronized.
  Therefore one clock domain can enter or leave the reset state before the other.
*/
 
module vga_fifo_dc (rclk, wclk, rclr, wclr, wreq, d, rreq, q, empty, full);
 
        // parameters
        parameter AWIDTH = 7;  //128 entries
        parameter DWIDTH = 16; //16bit databus
 
        // inputs & outputs
        input rclk;             // read clock
        input wclk;             // write clock
        input rclr;             // active high synchronous clear, synchronous to read clock
        input wclr;             // active high synchronous clear, synchronous to write clock
        input wreq;             // write request
        input [DWIDTH -1:0] d;  // data input
        input rreq;             // read request
        output [DWIDTH -1:0] q; // data output
 
        output empty;           // FIFO is empty, synchronous to read clock
        reg empty;
        output full;            // FIFO is full, synchronous to write clock
        reg full;
 
        // variable declarations
        reg rrst, wrst, srclr, ssrclr, swclr, sswclr;
        reg [AWIDTH -1:0] rptr, wptr, rptr_gray, wptr_gray;
 
        //
        // module body
        //
 
 
        function [AWIDTH:1] bin2gray;
                input [AWIDTH:1] bin;
                integer n;
        begin
                for (n=1; n<AWIDTH; n=n+1)
                        bin2gray[n] = bin[n+1] ^ bin[n];
 
                bin2gray[AWIDTH] = bin[AWIDTH];
        end
        endfunction
 
        function [AWIDTH:1] gray2bin;
                input [AWIDTH:1] gray;
        begin
                // same logic as bin2gray
                gray2bin = bin2gray(gray);
        end
        endfunction
 
        //
        // Pointers
        //
 
        // generate synchronized resets
        always @(posedge rclk)
        begin
            swclr  <= #1 wclr;
            sswclr <= #1 swclr;
            rrst   <= #1 rclr | sswclr;
        end
 
        always @(posedge wclk)
        begin
            srclr  <= #1 rclr;
            ssrclr <= #1 srclr;
            wrst   <= #1 wclr | ssrclr;
        end
 
 
        // read pointer
        always @(posedge rclk)
          if (rrst) begin
              rptr      <= #1 0;
              rptr_gray <= #1 0;
          end else if (rreq) begin
              rptr      <= #1 rptr +1'h1;
              rptr_gray <= #1 bin2gray(rptr +1'h1);
          end
 
        // write pointer
        always @(posedge wclk)
          if (wrst) begin
              wptr      <= #1 0;
              wptr_gray <= #1 0;
          end else if (wreq) begin
              wptr      <= #1 wptr +1'h1;
              wptr_gray <= #1 bin2gray(wptr +1'h1);
          end
 
        //
        // status flags
        //
        reg [AWIDTH-1:0] srptr_gray, ssrptr_gray;
        reg [AWIDTH-1:0] swptr_gray, sswptr_gray;
 
        // from one clock domain, to the other
        always @(posedge rclk)
        begin
            swptr_gray  <= #1 wptr_gray;
            sswptr_gray <= #1 swptr_gray;
        end
 
        always @(posedge wclk)
        begin
            srptr_gray  <= #1 rptr_gray;
            ssrptr_gray <= #1 srptr_gray;
        end
 
        // EMPTY
        // WC: wptr did not increase
        always @(posedge rclk)
          if (rrst)
            empty <= #1 1'b1;
          else if (rreq)
            empty <= #1 bin2gray(rptr +1'h1) == sswptr_gray;
          else
            empty <= #1 empty & (rptr_gray == sswptr_gray);
 
 
        // FULL
        // WC: rptr did not increase
        always @(posedge wclk)
          if (wrst)
            full <= #1 1'b0;
          else if (wreq)
            full <= #1 bin2gray(wptr +2'h2) == ssrptr_gray;
          else
            full <= #1 full & (bin2gray(wptr + 2'h1) == ssrptr_gray);
 
 
        // hookup generic dual ported memory
        generic_dpram #(AWIDTH, DWIDTH) fifo_dc_mem(
                .rclk(rclk),
                .rrst(1'b0),
                .rce(1'b1),
                .oe(1'b1),
                .raddr(rptr),
                .do(q),
                .wclk(wclk),
                .wrst(1'b0),
                .wce(1'b1),
                .we(wreq),
                .waddr(wptr),
                .di(d)
        );
 
endmodule

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant VGA/LCD Core; Dual Clocked Fifo ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	17	rherveille	`//`
40	57	rherveille	`// $Id: vga_fifo_dc.v,v 1.6 2003-08-01 11:46:38 rherveille Exp $`
41	17	rherveille	`//`
42	57	rherveille	`// $Date: 2003-08-01 11:46:38 $`
43			`// $Revision: 1.6 $`
44	23	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	57	rherveille	`// Revision 1.5 2003/05/07 09:48:54 rherveille`
51			`// Fixed some Wishbone RevB.3 related bugs.`
52			`// Changed layout of the core. Blocks are located more logically now.`
53			`// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.`
54			`//`
55	53	rherveille	`// Revision 1.4 2002/01/28 03:47:16 rherveille`
56			`// Changed counter-library.`
57			`// Changed vga-core.`
58			`// Added 32bpp mode.`
59			`//`
60	17	rherveille
61	53	rherveille	`//synopsys translate_off`
62	17	rherveille	`include "timescale.v"
63	53	rherveille	`//synopsys translate_on`
64	17	rherveille
65
66	57	rherveille	`/*`
67
68			`Dual clock FIFO.`
69
70			`Uses gray codes to move from one clock domain to the other.`
71
72			`Flags are synchronous to the related clock domain;`
73			`- empty: synchronous to read_clock`
74			`- full : synchronous to write_clock`
75
76			`CLR is available in both clock-domains.`
77			`Asserting any clr signal resets the entire FIFO.`
78			`When crossing clock domains the clears are synchronized.`
79			`Therefore one clock domain can enter or leave the reset state before the other.`
80			`*/`
81
82			`module vga_fifo_dc (rclk, wclk, rclr, wclr, wreq, d, rreq, q, empty, full);`
83
84	17	rherveille	`// parameters`
85			`parameter AWIDTH = 7; //128 entries`
86			`parameter DWIDTH = 16; //16bit databus`
87
88			`// inputs & outputs`
89			`input rclk; // read clock`
90			`input wclk; // write clock`
91	57	rherveille	`input rclr; // active high synchronous clear, synchronous to read clock`
92			`input wclr; // active high synchronous clear, synchronous to write clock`
93	17	rherveille	`input wreq; // write request`
94			`input [DWIDTH -1:0] d; // data input`
95			`input rreq; // read request`
96			`output [DWIDTH -1:0] q; // data output`
97
98	57	rherveille	`output empty; // FIFO is empty, synchronous to read clock`
99			`reg empty;`
100			`output full; // FIFO is full, synchronous to write clock`
101			`reg full;`
102	17	rherveille
103			`// variable declarations`
104	57	rherveille	`reg rrst, wrst, srclr, ssrclr, swclr, sswclr;`
105			`reg [AWIDTH -1:0] rptr, wptr, rptr_gray, wptr_gray;`
106	17	rherveille
107			`//`
108			`// module body`
109			`//`
110
111
112	57	rherveille	`function [AWIDTH:1] bin2gray;`
113			`input [AWIDTH:1] bin;`
114			`integer n;`
115			`begin`
116			`for (n=1; n<AWIDTH; n=n+1)`
117			`bin2gray[n] = bin[n+1] ^ bin[n];`
118
119			`bin2gray[AWIDTH] = bin[AWIDTH];`
120			`end`
121			`endfunction`
122
123			`function [AWIDTH:1] gray2bin;`
124			`input [AWIDTH:1] gray;`
125			`begin`
126			`// same logic as bin2gray`
127			`gray2bin = bin2gray(gray);`
128			`end`
129			`endfunction`
130
131	17	rherveille	`//`
132			`// Pointers`
133			`//`
134	57	rherveille
135			`// generate synchronized resets`
136			`always @(posedge rclk)`
137			`begin`
138			`swclr <= #1 wclr;`
139			`sswclr <= #1 swclr;`
140			`rrst <= #1 rclr \| sswclr;`
141			`end`
142
143			`always @(posedge wclk)`
144			`begin`
145			`srclr <= #1 rclr;`
146			`ssrclr <= #1 srclr;`
147			`wrst <= #1 wclr \| ssrclr;`
148			`end`
149
150
151	17	rherveille	`// read pointer`
152	57	rherveille	`always @(posedge rclk)`
153			`if (rrst) begin`
154			`rptr <= #1 0;`
155			`rptr_gray <= #1 0;`
156			`end else if (rreq) begin`
157			`rptr <= #1 rptr +1'h1;`
158			`rptr_gray <= #1 bin2gray(rptr +1'h1);`
159			`end`
160	17	rherveille
161			`// write pointer`
162	57	rherveille	`always @(posedge wclk)`
163			`if (wrst) begin`
164			`wptr <= #1 0;`
165			`wptr_gray <= #1 0;`
166			`end else if (wreq) begin`
167			`wptr <= #1 wptr +1'h1;`
168			`wptr_gray <= #1 bin2gray(wptr +1'h1);`
169			`end`
170	17	rherveille
171			`//`
172			`// status flags`
173			`//`
174	57	rherveille	`reg [AWIDTH-1:0] srptr_gray, ssrptr_gray;`
175			`reg [AWIDTH-1:0] swptr_gray, sswptr_gray;`
176	17	rherveille
177	57	rherveille	`// from one clock domain, to the other`
178			`always @(posedge rclk)`
179			`begin`
180			`swptr_gray <= #1 wptr_gray;`
181			`sswptr_gray <= #1 swptr_gray;`
182			`end`
183	17	rherveille
184	57	rherveille	`always @(posedge wclk)`
185			`begin`
186			`srptr_gray <= #1 rptr_gray;`
187			`ssrptr_gray <= #1 srptr_gray;`
188			`end`
189	17	rherveille
190	57	rherveille	`// EMPTY`
191			`// WC: wptr did not increase`
192			`always @(posedge rclk)`
193			`if (rrst)`
194			`empty <= #1 1'b1;`
195			`else if (rreq)`
196			`empty <= #1 bin2gray(rptr +1'h1) == sswptr_gray;`
197			`else`
198			`empty <= #1 empty & (rptr_gray == sswptr_gray);`
199	17	rherveille
200	57	rherveille
201			`// FULL`
202			`// WC: rptr did not increase`
203			`always @(posedge wclk)`
204			`if (wrst)`
205			`full <= #1 1'b0;`
206			`else if (wreq)`
207			`full <= #1 bin2gray(wptr +2'h2) == ssrptr_gray;`
208			`else`
209			`full <= #1 full & (bin2gray(wptr + 2'h1) == ssrptr_gray);`
210
211
212	17	rherveille	`// hookup generic dual ported memory`
213			`generic_dpram #(AWIDTH, DWIDTH) fifo_dc_mem(`
214			`.rclk(rclk),`
215			`.rrst(1'b0),`
216			`.rce(1'b1),`
217			`.oe(1'b1),`
218			`.raddr(rptr),`
219			`.do(q),`
220			`.wclk(wclk),`
221			`.wrst(1'b0),`
222			`.wce(1'b1),`
223			`.we(wreq),`
224			`.waddr(wptr),`
225			`.di(d)`
226			`);`
227
228			`endmodule`

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo_dc.v] - Blame information for rev 62