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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_vtim.v] - Blame information for rev 62

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant VGA/LCD Core; Timing Generator   ////
////  Video Timing Generator                                     ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/vga_lcd ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_vtim.v,v 1.8 2003-05-07 09:48:54 rherveille Exp $
//
//  $Date: 2003-05-07 09:48:54 $
//  $Revision: 1.8 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.7  2003/03/19 12:50:45  rherveille
//               Changed timing generator; made it smaller and easier.
//
//               Revision 1.6  2002/04/20 10:02:39  rherveille
//               Changed video timing generator.
//               Changed wishbone master vertical gate count code.
//               Fixed a potential bug in the wishbone slave (cursor color register readout).
//
//               Revision 1.5  2002/01/28 03:47:16  rherveille
//               Changed counter-library.
//               Changed vga-core.
//               Added 32bpp mode.
//
 
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
 
module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
        // inputs & outputs
        input clk; // master clock
        input ena; // count enable
        input rst; // synchronous active high reset
 
        input [ 7:0] Tsync; // sync duration
        input [ 7:0] Tgdel; // gate delay
        input [15:0] Tgate; // gate length
        input [15:0] Tlen;  // line time / frame time
 
        output Sync; // synchronization pulse
        output Gate; // gate
        output Done; // done with line/frame
        reg Sync;
        reg Gate;
        reg Done;
 
        //
        // module body
        //
 
        // generate timing statemachine
        reg  [15:0] cnt, cnt_len;
        wire [16:0] cnt_nxt, cnt_len_nxt;
        wire        cnt_done, cnt_len_done;
 
        assign cnt_nxt = {1'b0, cnt} -17'h1;
        assign cnt_done = cnt_nxt[16];
 
        assign cnt_len_nxt = {1'b0, cnt_len} -17'h1;
        assign cnt_len_done = cnt_len_nxt[16];
 
        reg [4:0] state;
        parameter [4:0] idle_state = 5'b00001;
        parameter [4:0] sync_state = 5'b00010;
        parameter [4:0] gdel_state = 5'b00100;
        parameter [4:0] gate_state = 5'b01000;
        parameter [4:0] len_state  = 5'b10000;
 
        always @(posedge clk)
          if (rst)
            begin
                state   <= #1 idle_state;
                cnt     <= #1 16'h0;
                cnt_len <= #1 16'b0;
                Sync    <= #1 1'b0;
                Gate    <= #1 1'b0;
                Done    <= #1 1'b0;
            end
          else if (ena)
            begin
                cnt     <= #1 cnt_nxt[15:0];
                cnt_len <= #1 cnt_len_nxt[15:0];
 
                Done    <= #1 1'b0;
 
                case (state) // synopsys full_case parallel_case
                  idle_state:
                    begin
                        state   <= #1 sync_state;
                        cnt     <= #1 Tsync;
                        cnt_len <= #1 Tlen;
 
                        Sync    <= #1 1'b1;
                    end
 
                  sync_state:
                    if (cnt_done)
                      begin
                          state <= #1 gdel_state;
                          cnt   <= #1 Tgdel;
 
                          Sync  <= #1 1'b0;
                      end
 
                  gdel_state:
                    if (cnt_done)
                      begin
                          state <= #1 gate_state;
                          cnt   <= #1 Tgate;
 
                          Gate  <= #1 1'b1;
                      end
 
                  gate_state:
                    if (cnt_done)
                      begin
                          state <= #1 len_state;
 
                          Gate  <= #1 1'b0;
                      end
 
                  len_state:
                    if (cnt_len_done)
                      begin
                          state   <= #1 sync_state;
                          cnt     <= #1 Tsync;
                          cnt_len <= #1 Tlen;
 
                          Sync    <= #1 1'b1;
                          Done    <= #1 1'b1;
                      end
 
                endcase
            end
endmodule

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant VGA/LCD Core; Timing Generator ////`
4			`//// Video Timing Generator ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	17	rherveille	`//`
40	53	rherveille	`// $Id: vga_vtim.v,v 1.8 2003-05-07 09:48:54 rherveille Exp $`
41	17	rherveille	`//`
42	53	rherveille	`// $Date: 2003-05-07 09:48:54 $`
43			`// $Revision: 1.8 $`
44	23	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	53	rherveille	`// Revision 1.7 2003/03/19 12:50:45 rherveille`
51			`// Changed timing generator; made it smaller and easier.`
52			`//`
53	45	rherveille	`// Revision 1.6 2002/04/20 10:02:39 rherveille`
54			`// Changed video timing generator.`
55			`// Changed wishbone master vertical gate count code.`
56			`// Fixed a potential bug in the wishbone slave (cursor color register readout).`
57			`//`
58	39	rherveille	`// Revision 1.5 2002/01/28 03:47:16 rherveille`
59			`// Changed counter-library.`
60			`// Changed vga-core.`
61			`// Added 32bpp mode.`
62			`//`
63	17	rherveille
64	53	rherveille	`//synopsys translate_off`
65	17	rherveille	`include "timescale.v"
66	53	rherveille	`//synopsys translate_on`
67	17	rherveille
68			`module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);`
69			`// inputs & outputs`
70			`input clk; // master clock`
71			`input ena; // count enable`
72			`input rst; // synchronous active high reset`
73
74			`input [ 7:0] Tsync; // sync duration`
75			`input [ 7:0] Tgdel; // gate delay`
76			`input [15:0] Tgate; // gate length`
77			`input [15:0] Tlen; // line time / frame time`
78
79			`output Sync; // synchronization pulse`
80			`output Gate; // gate`
81			`output Done; // done with line/frame`
82			`reg Sync;`
83			`reg Gate;`
84	45	rherveille	`reg Done;`
85	17	rherveille
86			`//`
87			`// module body`
88			`//`
89
90	45	rherveille	`// generate timing statemachine`
91			`reg [15:0] cnt, cnt_len;`
92			`wire [16:0] cnt_nxt, cnt_len_nxt;`
93			`wire cnt_done, cnt_len_done;`
94	17	rherveille
95	45	rherveille	`assign cnt_nxt = {1'b0, cnt} -17'h1;`
96			`assign cnt_done = cnt_nxt[16];`
97	17	rherveille
98	45	rherveille	`assign cnt_len_nxt = {1'b0, cnt_len} -17'h1;`
99			`assign cnt_len_done = cnt_len_nxt[16];`
100	17	rherveille
101	45	rherveille	`reg [4:0] state;`
102			`parameter [4:0] idle_state = 5'b00001;`
103			`parameter [4:0] sync_state = 5'b00010;`
104			`parameter [4:0] gdel_state = 5'b00100;`
105			`parameter [4:0] gate_state = 5'b01000;`
106			`parameter [4:0] len_state = 5'b10000;`
107	17	rherveille
108	45	rherveille	`always @(posedge clk)`
109			`if (rst)`
110			`begin`
111			`state <= #1 idle_state;`
112			`cnt <= #1 16'h0;`
113			`cnt_len <= #1 16'b0;`
114			`Sync <= #1 1'b0;`
115			`Gate <= #1 1'b0;`
116			`Done <= #1 1'b0;`
117			`end`
118			`else if (ena)`
119			`begin`
120			`cnt <= #1 cnt_nxt[15:0];`
121			`cnt_len <= #1 cnt_len_nxt[15:0];`
122	17	rherveille
123	45	rherveille	`Done <= #1 1'b0;`
124	17	rherveille
125	53	rherveille	`case (state) // synopsys full_case parallel_case`
126	45	rherveille	`idle_state:`
127			`begin`
128			`state <= #1 sync_state;`
129			`cnt <= #1 Tsync;`
130			`cnt_len <= #1 Tlen;`
131	17	rherveille
132	45	rherveille	`Sync <= #1 1'b1;`
133			`end`
134
135			`sync_state:`
136			`if (cnt_done)`
137			`begin`
138			`state <= #1 gdel_state;`
139			`cnt <= #1 Tgdel;`
140
141			`Sync <= #1 1'b0;`
142			`end`
143
144			`gdel_state:`
145			`if (cnt_done)`
146			`begin`
147			`state <= #1 gate_state;`
148			`cnt <= #1 Tgate;`
149
150			`Gate <= #1 1'b1;`
151			`end`
152
153			`gate_state:`
154			`if (cnt_done)`
155			`begin`
156			`state <= #1 len_state;`
157
158			`Gate <= #1 1'b0;`
159			`end`
160
161			`len_state:`
162			`if (cnt_len_done)`
163			`begin`
164			`state <= #1 sync_state;`
165			`cnt <= #1 Tsync;`
166			`cnt_len <= #1 Tlen;`
167
168			`Sync <= #1 1'b1;`
169			`Done <= #1 1'b1;`
170			`end`
171
172			`endcase`
173			`end`
174	17	rherveille	`endmodule`

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_vtim.v] - Blame information for rev 62