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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant enhanced VGA/LCD Core            ////
////  Wishbone master interface                                  ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/vga_lcd ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_wb_master.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
//
//  $Date: 2002-02-07 05:42:10 $
//  $Revision: 1.6 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
 
`include "timescale.v"
`include "vga_defines.v"
 
module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
        ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw,
        cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
        VBAa, VBAb, Thgate, Tvgate,
        stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full,
        clut_req, clut_ack, clut_adr, clut_q);
 
        // inputs & outputs
 
        // wishbone signals
        input         clk_i;    // master clock input
        input         rst_i;    // synchronous active high reset
        input         nrst_i;   // asynchronous low reset
        output        cyc_o;    // cycle output
        reg cyc_o;
        output        stb_o;    // strobe ouput
        reg stb_o;
        output        cab_o;    // consecutive address burst output
        reg cab_o;
        output        we_o;     // write enable output
        reg we_o;
        output [31:0] adr_o;    // address output
        output [ 3:0] sel_o;    // byte select outputs (only 32bits accesses are supported)
        reg [3:0] sel_o;
        input         ack_i;    // wishbone cycle acknowledge 
        input         err_i;    // wishbone cycle error
        input [31:0]  dat_i;    // wishbone data in
 
        output        sint;     // non recoverable error, interrupt host
 
        // control register settings
        input       ctrl_ven;   // video enable bit
        input [1:0] ctrl_cd;    // color depth
        input       ctrl_pc;    // 8bpp pseudo color/bw
        input [1:0] ctrl_vbl;   // burst length
        input       ctrl_vbsw;  // enable video bank switching
        input       ctrl_cbsw;  // enable clut bank switching
 
        input         cursor0_en; // enable hardware cursor0
        input [31: 0] cursor0_xy; // (x,y) address hardware cursor0
        input [31:11] cursor0_ba; // cursor0 video memory base address
        input         cursor0_ld; // reload cursor0 from video memory
        input         cursor1_en; // enable hardware cursor1
        input [31: 0] cursor1_xy; // (x,y) address hardware cursor1
        input [31:11] cursor1_ba; // cursor1 video memory base address
        input         cursor1_ld; // reload cursor1 from video memory
 
        // video memory addresses
        input [31: 2] VBAa;     // video memory base address A
        input [31: 2] VBAb;     // video memory base address B
 
        input [15:0] Thgate;    // horizontal visible area (in pixels)
        input [15:0] Tvgate;    // vertical visible area (in horizontal lines)
 
        output stat_avmp;       // active video memory page
        output stat_acmp;       // active CLUT memory page
        reg stat_acmp;
        output vmem_switch;     // video memory bank-switch request: memory page switched (when enabled)
        output clut_switch;     // clut memory bank-switch request: clut page switched (when enabled)
 
        // to/from line-fifo
        output        line_fifo_wreq;
        output [23:0] line_fifo_d;
        input         line_fifo_full;
 
        // to/from color lookup-table
        output        clut_req;  // clut access request
        input         clut_ack;  // clut access acknowledge
        output [ 8:0] clut_adr;  // clut access address
        input  [23:0] clut_q;    // clut access data in
 
        //
        // variable declarations
        //
 
        reg vmem_acc;                 // video memory access
        wire nvmem_req, vmem_ack;     // NOT video memory access request // video memory access acknowledge
 
        wire ImDone;                  // Done reading image from video mem 
        reg  dImDone;                 // delayed ImDone
        wire  ImDoneStrb;             // image done (strobe signal)
        reg  dImDoneStrb;             // delayed ImDoneStrb
 
        wire data_fifo_rreq, data_fifo_empty, data_fifo_hfull;
        wire [31:0] data_fifo_q;
        wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d;
        wire        color_proc_wreq, ssel1_wreq, rgb_fifo_wreq;
        wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq;
        wire ImDoneFifoQ;
        reg  dImDoneFifoQ, ddImDoneFifoQ;
        reg  [2:0] ImDoneCursorQ;
 
        reg sclr; // synchronous clear
 
        wire [7:0] clut_offs; // color lookup table offset
 
        reg [8:0] cursor_adr;
        reg       cursor0_we, cursor1_we;
 
        //
        // module body
        //
 
        // generate synchronous clear
        always@(posedge clk_i)
                sclr <= #1 ~ctrl_ven;
 
        //
        // WISHBONE block
        //
        reg  [ 2:0] burst_cnt;                       // video memory burst access counter
        wire        burst_done;                      // completed burst access to video mem
        reg         sel_VBA;                         // select video memory base address
        reg  [31:2] vmemA;                           // video memory address 
 
        // wishbone access controller, video memory access request has highest priority (try to keep fifo full)
        always@(posedge clk_i)
                if (sclr)
                        vmem_acc <= #1 1'b0;
                else
                        vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone;
 
        assign vmem_ack = ack_i;
        assign sint = err_i; // Non recoverable error, interrupt host system
 
        // select active memory page
        assign vmem_switch = ImDoneStrb;
 
        always@(posedge clk_i)
                if (sclr)
                        sel_VBA <= #1 1'b0;
                else if (ctrl_vbsw)
                        sel_VBA <= #1 sel_VBA ^ vmem_switch;  // select next video memory bank when finished reading current bank (and bank switch enabled)
 
        assign stat_avmp = sel_VBA; // assign output
 
        // selecting active clut page / cursor data
        // delay image done same amount as video-memory data
        vga_fifo #(4, 1) clut_sw_fifo (
                .clk(clk_i),
                .aclr(1'b1),
                .sclr(sclr),
                .d(ImDone),
                .wreq(vmem_ack),
                .q(ImDoneFifoQ),
                .rreq(data_fifo_rreq),
                .empty(),
                .hfull(),
                .full()
        );
 
        // clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay
        always@(posedge clk_i)
                if (sclr)
                        dImDoneFifoQ <= #1 1'b0;
                else    if (data_fifo_rreq)
                        dImDoneFifoQ <= #1 ImDoneFifoQ;
 
        always@(posedge clk_i)
                if (sclr)
                        ddImDoneFifoQ <= #1 1'b0;
                else
                        ddImDoneFifoQ <= #1 dImDoneFifoQ;
 
        assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ;
 
        always@(posedge clk_i)
                if (sclr)
                        stat_acmp <= #1 1'b0;
                else if (ctrl_cbsw)
                        stat_acmp <= #1 stat_acmp ^ clut_switch;  // select next clut when finished reading clut for current video bank (and bank switch enabled)
 
        // generate clut-address
        assign clut_adr = {stat_acmp, clut_offs};
 
        // generate burst counter
        wire [3:0] burst_cnt_val;
        assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
        assign burst_done = burst_cnt_val[3];
 
        always@(posedge clk_i)
                if ( (burst_done & vmem_ack) | !vmem_acc)
                        case (ctrl_vbl) // synopsis full_case parallel_case
                                2'b00: burst_cnt <= #1 3'b000; // burst length 1
                                2'b01: burst_cnt <= #1 3'b001; // burst length 2
                                2'b10: burst_cnt <= #1 3'b011; // burst length 4
                                2'b11: burst_cnt <= #1 3'b111; // burst length 8
                        endcase
                else if(vmem_ack)
                        burst_cnt <= #1 burst_cnt_val[2:0];
 
        //
        // generate image counters
        //
 
        // hgate counter
        reg  [15:0] hgate_cnt;
        reg  [16:0] hgate_cnt_val;
        reg  [1:0]  hgate_div_cnt;
        reg  [2:0]  hgate_div_val;
 
        wire hdone = hgate_cnt_val[16] & vmem_ack; // ????
 
        always@(hgate_cnt or hgate_div_cnt or ctrl_cd)
                begin
                        hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;
 
                        if (ctrl_cd != 2'b10)
                                hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
                        else if ( hgate_div_val[2] )
                                hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
                        else
                                hgate_cnt_val = {1'b0, hgate_cnt};
                end
 
        always@(posedge clk_i)
                if (sclr)
                                begin
                                        case(ctrl_cd) // synopsys full_case parallel_case
                                                2'b00: // 8bpp
                                                        hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle
                                                2'b01: //16bpp
                                                        hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle
                                                2'b10: //24bpp
                                                        hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle
                                                2'b11: //32bpp
                                                        hgate_cnt <= #1 Thgate;      // 1 pixel per cycle
                                        endcase
 
                                        hgate_div_cnt <= 2'b10;
                                end
                else if (vmem_ack)
                        if (hdone)
                                begin
                                        case(ctrl_cd) // synopsys full_case parallel_case
                                                2'b00: // 8bpp
                                                        hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle
                                                2'b01: //16bpp
                                                        hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle
                                                2'b10: //24bpp
                                                        hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle
                                                2'b11: //32bpp
                                                        hgate_cnt <= #1 Thgate;      // 1 pixel per cycle
                                        endcase
                                        hgate_div_cnt <= #1 2'b10;
                                end
                        else //if (vmem_ack)
                                begin
                                        hgate_cnt <= #1 hgate_cnt_val[15:0];
 
                                        if ( hgate_div_val[2] )
                                                hgate_div_cnt <= #1 2'b10;
                                        else
                                                hgate_div_cnt <= #1 hgate_div_val[1:0];
                                end
 
        // vgate counter
        reg  [15:0] vgate_cnt;
        wire [16:0] vgate_cnt_val = {1'b0, vgate_cnt} -17'h1;
        wire vdone = vgate_cnt_val[16];
 
        always@(posedge clk_i)
                if (sclr)
                        vgate_cnt <= #1 Tvgate;
                else if (ImDoneStrb)
                        vgate_cnt <= #1 Tvgate;
                else if (hdone)
                        vgate_cnt <= #1 vgate_cnt_val[15:0];
 
        assign ImDone = hdone & vdone;
 
        assign ImDoneStrb = ImDone & !dImDone;
 
        always@(posedge clk_i)
                begin
                        dImDone <= #1 ImDone;
                        dImDoneStrb <= #1 ImDoneStrb;
                end
 
        //
        // generate addresses
        //
 
        // select video memory base address
        always@(posedge clk_i)
                if (dImDoneStrb | sclr)
                        if (!sel_VBA)
                                vmemA <= #1 VBAa;
                        else
                                vmemA <= #1 VBAb;
                else if (vmem_ack)
                        vmemA <= #1 vmemA +30'h1;
 
        // generate wishbone signals
        assign adr_o = {vmemA, 2'b00};
        wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone;
 
        always@(posedge clk_i or negedge nrst_i)
                if (!nrst_i)
                        begin
                                cyc_o <= #1 1'b0;
                                stb_o <= #1 1'b0;
                                sel_o <= #1 4'b1111;
                                cab_o <= #1 1'b0;
                                we_o  <= #1 1'b0;
                        end
                else
                        if (rst_i)
                                begin
                                        cyc_o <= #1 1'b0;
                                        stb_o <= #1 1'b0;
                                        sel_o <= #1 4'b1111;
                                        cab_o <= #1 1'b0;
                                        we_o  <= #1 1'b0;
                                end
                        else
                                begin
                                        cyc_o <= #1 wb_cycle;
                                        stb_o <= #1 wb_cycle;
                                        sel_o <= #1 4'b1111;   // only 32bit accesses are supported
                                        cab_o <= #1 wb_cycle;
                                        we_o  <= #1 1'b0;      // read only
                                end
 
        // video-data buffer (temporary store data read from video memory)
        vga_fifo #(4, 32) data_fifo (
                .clk(clk_i),
                .aclr(1'b1),
                .sclr(sclr),
                .d(dat_i),
                .wreq(vmem_ack),
                .q(data_fifo_q),
                .rreq(data_fifo_rreq),
                .empty(data_fifo_empty),
                .hfull(data_fifo_hfull),
                .full()
        );
 
        assign nvmem_req = data_fifo_hfull;
 
 
        // hookup color processor
        vga_colproc color_proc (
                .clk(clk_i),
                .srst(sclr),
                .vdat_buffer_di(data_fifo_q),
                .ColorDepth(ctrl_cd),
                .PseudoColor(ctrl_pc),
                .vdat_buffer_empty(data_fifo_empty),
                .vdat_buffer_rreq(data_fifo_rreq),
                .rgb_fifo_full(rgb_fifo_full),
                .rgb_fifo_wreq(color_proc_wreq),
                .r(color_proc_q[23:16]),
                .g(color_proc_q[15:8]),
                .b(color_proc_q[7:0]),
                .clut_req(clut_req),
                .clut_ack(clut_ack),
                .clut_offs(clut_offs),
                .clut_q(clut_q)
        );
 
        // hookup data-source-selector && hardware cursor module
`ifdef VGA_HWC1
        reg scursor1_ld;
        reg scursor1_en;
        reg [31:0] scursor1_xy;
        reg sddImDoneFifoQ, sdImDoneFifoQ;
 
        always@(posedge clk_i)
                if (ssel1_wreq)
                        begin
                                sdImDoneFifoQ  <= #1 dImDoneFifoQ;
                                sddImDoneFifoQ <= #1 sdImDoneFifoQ;
                        end
 
        always@(posedge clk_i)
                if (sclr)
                        scursor1_ld <= #1 1'b0;
                else
                        scursor1_ld <= #1 cursor1_ld | (scursor1_ld & !(ddImDoneFifoQ & !dImDoneFifoQ));
 
        always@(posedge clk_i)
                if (sclr)
                        scursor1_en <= #1 1'b0;
                else if (scursor1_ld)
                        scursor1_en <= #1 cursor1_en;
 
        always@(posedge clk_i)
                if (scursor1_ld)
                        scursor1_xy <= #1 cursor1_xy;
 
        vga_ssel ssel_and_hw_cursor1 (
                .clk(clk_i),
                .rst_i(sclr),
                .Thgate(Thgate),
                .Tvgate(Tvgate),
                .idat(color_proc_q),
                .idat_wreq(color_proc_wreq),
                .cursor_xy(scursor1_xy),
                .cursor_en(scursor1_en),
                .cursor_adr(cursor_adr),
                .cursor_we(cursor1_we),
                .cursor_dat(dat_i),
                .rgb_fifo_wreq(ssel1_wreq),
                .rgb(ssel1_q)
        );
`else
        wire sddImDoneFifoQ, sdImDoneFifoQ;
 
        assign ssel1_wreq = color_proc_wreq;
        assign ssel1_q    = color_proc_q;
 
        assign sdImDoneFifoQ  = dImDoneFifoQ;
        assign sddImDoneFifoQ = ddImDoneFifoQ;
`endif
 
`ifdef VGA_HWC0
        reg scursor0_ld;
        reg scursor0_en;
        reg [31:0] scursor0_xy;
 
        always@(posedge clk_i)
                if (sclr)
                        scursor0_ld <= #1 1'b0;
                else
                        scursor0_ld <= #1 cursor0_ld | (scursor0_ld & !(sddImDoneFifoQ & !sdImDoneFifoQ));
 
        always@(posedge clk_i)
                if (sclr)
                        scursor0_en <= #1 1'b0;
                else if (scursor0_ld)
                        scursor0_en <= #1 cursor0_en;
 
        always@(posedge clk_i)
                if (scursor0_ld)
                        scursor0_xy <= #1 cursor0_xy;
 
        vga_ssel ssel_and_hw_cursor0 (
                .clk(clk_i),
                .rst_i(sclr),
                .Thgate(Thgate),
                .Tvgate(Tvgate),
                .idat(ssel1_q),
                .idat_wreq(ssel1_wreq),
                .cursor_xy(scursor0_xy),
                .cursor_en(scursor0_en),
                .cursor_adr(cursor_adr),
                .cursor_we(cursor0_we),
                .cursor_dat(dat_i),
                .rgb_fifo_wreq(rgb_fifo_wreq),
                .rgb(rgb_fifo_d)
        );
`else
        assign rgb_fifo_wreq = ssel1_wreq;
        assign rgb_fifo_d = ssel1_q;
`endif
 
        // hookup RGB buffer (temporary station between WISHBONE-clock-domain and pixel-clock-domain)
        vga_fifo #(3, 24) rgb_fifo (
                .clk(clk_i),
                .aclr(1'b1),
                .sclr(sclr),
                .d(rgb_fifo_d),
                .wreq(rgb_fifo_wreq),
                .q(line_fifo_d),
                .rreq(rgb_fifo_rreq),
                .empty(rgb_fifo_empty),
                .hfull(rgb_fifo_full),
                .full()
        );
 
        assign rgb_fifo_rreq = !line_fifo_full && !rgb_fifo_empty;
        assign line_fifo_wreq = rgb_fifo_rreq;
 
endmodule
 
 
 
 

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	30	rherveille	`//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////`
4	23	rherveille	`//// Wishbone master interface ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	30	rherveille	`//// Copyright (C) 2001, 2002 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16	23	rherveille	`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	17	rherveille	`//`
40	30	rherveille	`// $Id: vga_wb_master.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $`
41	17	rherveille	`//`
42	30	rherveille	`// $Date: 2002-02-07 05:42:10 $`
43			`// $Revision: 1.6 $`
44	23	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	17	rherveille
51			`include "timescale.v"
52	30	rherveille	`include "vga_defines.v"
53	17	rherveille
54	19	rherveille	`module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,`
55	30	rherveille	`ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw,`
56			`cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,`
57			`VBAa, VBAb, Thgate, Tvgate,`
58	19	rherveille	`stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full,`
59			`clut_req, clut_ack, clut_adr, clut_q);`
60	17	rherveille
61			`// inputs & outputs`
62
63			`// wishbone signals`
64	19	rherveille	`input clk_i; // master clock input`
65			`input rst_i; // synchronous active high reset`
66			`input nrst_i; // asynchronous low reset`
67			`output cyc_o; // cycle output`
68			`reg cyc_o;`
69			`output stb_o; // strobe ouput`
70			`reg stb_o;`
71			`output cab_o; // consecutive address burst output`
72			`reg cab_o;`
73			`output we_o; // write enable output`
74			`reg we_o;`
75			`output [31:0] adr_o; // address output`
76			`output [ 3:0] sel_o; // byte select outputs (only 32bits accesses are supported)`
77			`reg [3:0] sel_o;`
78			`input ack_i; // wishbone cycle acknowledge`
79			`input err_i; // wishbone cycle error`
80			`input [31:0] dat_i; // wishbone data in`
81	17	rherveille
82	19	rherveille	`output sint; // non recoverable error, interrupt host`
83	17	rherveille
84			`// control register settings`
85			`input ctrl_ven; // video enable bit`
86			`input [1:0] ctrl_cd; // color depth`
87			`input ctrl_pc; // 8bpp pseudo color/bw`
88			`input [1:0] ctrl_vbl; // burst length`
89			`input ctrl_vbsw; // enable video bank switching`
90			`input ctrl_cbsw; // enable clut bank switching`
91
92	30	rherveille	`input cursor0_en; // enable hardware cursor0`
93			`input [31: 0] cursor0_xy; // (x,y) address hardware cursor0`
94			`input [31:11] cursor0_ba; // cursor0 video memory base address`
95			`input cursor0_ld; // reload cursor0 from video memory`
96			`input cursor1_en; // enable hardware cursor1`
97			`input [31: 0] cursor1_xy; // (x,y) address hardware cursor1`
98			`input [31:11] cursor1_ba; // cursor1 video memory base address`
99			`input cursor1_ld; // reload cursor1 from video memory`
100
101	17	rherveille	`// video memory addresses`
102			`input [31: 2] VBAa; // video memory base address A`
103			`input [31: 2] VBAb; // video memory base address B`
104
105			`input [15:0] Thgate; // horizontal visible area (in pixels)`
106			`input [15:0] Tvgate; // vertical visible area (in horizontal lines)`
107
108			`output stat_avmp; // active video memory page`
109			`output stat_acmp; // active CLUT memory page`
110	19	rherveille	`reg stat_acmp;`
111			`output vmem_switch; // video memory bank-switch request: memory page switched (when enabled)`
112			`output clut_switch; // clut memory bank-switch request: clut page switched (when enabled)`
113	17	rherveille
114			`// to/from line-fifo`
115			`output line_fifo_wreq;`
116			`output [23:0] line_fifo_d;`
117			`input line_fifo_full;`
118
119	19	rherveille	`// to/from color lookup-table`
120			`output clut_req; // clut access request`
121			`input clut_ack; // clut access acknowledge`
122			`output [ 8:0] clut_adr; // clut access address`
123			`input [23:0] clut_q; // clut access data in`
124
125	17	rherveille	`//`
126			`// variable declarations`
127			`//`
128	19	rherveille
129			`reg vmem_acc; // video memory access`
130	17	rherveille	`wire nvmem_req, vmem_ack; // NOT video memory access request // video memory access acknowledge`
131
132	30	rherveille	`wire ImDone; // Done reading image from video mem`
133	19	rherveille	`reg dImDone; // delayed ImDone`
134			`wire ImDoneStrb; // image done (strobe signal)`
135			`reg dImDoneStrb; // delayed ImDoneStrb`
136
137			`wire data_fifo_rreq, data_fifo_empty, data_fifo_hfull;`
138			`wire [31:0] data_fifo_q;`
139	30	rherveille	`wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d;`
140			`wire color_proc_wreq, ssel1_wreq, rgb_fifo_wreq;`
141			`wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq;`
142	19	rherveille	`wire ImDoneFifoQ;`
143	30	rherveille	`reg dImDoneFifoQ, ddImDoneFifoQ;`
144			`reg [2:0] ImDoneCursorQ;`
145	19	rherveille
146			`reg sclr; // synchronous clear`
147
148			`wire [7:0] clut_offs; // color lookup table offset`
149
150	30	rherveille	`reg [8:0] cursor_adr;`
151			`reg cursor0_we, cursor1_we;`
152
153	17	rherveille	`//`
154			`// module body`
155			`//`
156
157	19	rherveille	`// generate synchronous clear`
158			`always@(posedge clk_i)`
159			`sclr <= #1 ~ctrl_ven;`
160	17	rherveille
161			`//`
162			`// WISHBONE block`
163			`//`
164			`reg [ 2:0] burst_cnt; // video memory burst access counter`
165			`wire burst_done; // completed burst access to video mem`
166	19	rherveille	`reg sel_VBA; // select video memory base address`
167	17	rherveille	`reg [31:2] vmemA; // video memory address`
168
169			`// wishbone access controller, video memory access request has highest priority (try to keep fifo full)`
170	19	rherveille	`always@(posedge clk_i)`
171			`if (sclr)`
172			`vmem_acc <= #1 1'b0;`
173	17	rherveille	`else`
174	19	rherveille	`vmem_acc <= #1 (!nvmem_req \| (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone;`
175	17	rherveille
176	19	rherveille	`assign vmem_ack = ack_i;`
177			`assign sint = err_i; // Non recoverable error, interrupt host system`
178	17	rherveille
179	19	rherveille	`// select active memory page`
180			`assign vmem_switch = ImDoneStrb;`
181	17	rherveille
182	19	rherveille	`always@(posedge clk_i)`
183			`if (sclr)`
184	17	rherveille	`sel_VBA <= #1 1'b0;`
185			`else if (ctrl_vbsw)`
186	19	rherveille	`sel_VBA <= #1 sel_VBA ^ vmem_switch; // select next video memory bank when finished reading current bank (and bank switch enabled)`
187	17	rherveille
188			`assign stat_avmp = sel_VBA; // assign output`
189
190	30	rherveille	`// selecting active clut page / cursor data`
191			`// delay image done same amount as video-memory data`
192	19	rherveille	`vga_fifo #(4, 1) clut_sw_fifo (`
193			`.clk(clk_i),`
194			`.aclr(1'b1),`
195			`.sclr(sclr),`
196			`.d(ImDone),`
197	30	rherveille	`.wreq(vmem_ack),`
198	19	rherveille	`.q(ImDoneFifoQ),`
199			`.rreq(data_fifo_rreq),`
200			`.empty(),`
201			`.hfull(),`
202			`.full()`
203			`);`
204
205	30	rherveille	`// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay`
206	19	rherveille	`always@(posedge clk_i)`
207	30	rherveille	`if (sclr)`
208			`dImDoneFifoQ <= #1 1'b0;`
209			`else if (data_fifo_rreq)`
210	19	rherveille	`dImDoneFifoQ <= #1 ImDoneFifoQ;`
211
212			`always@(posedge clk_i)`
213			`if (sclr)`
214	30	rherveille	`ddImDoneFifoQ <= #1 1'b0;`
215			`else`
216			`ddImDoneFifoQ <= #1 dImDoneFifoQ;`
217	19	rherveille
218	30	rherveille	`assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ;`
219	19	rherveille
220			`always@(posedge clk_i)`
221			`if (sclr)`
222			`stat_acmp <= #1 1'b0;`
223	17	rherveille	`else if (ctrl_cbsw)`
224	19	rherveille	`stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled)`
225	17	rherveille
226	19	rherveille	`// generate clut-address`
227			`assign clut_adr = {stat_acmp, clut_offs};`
228	17	rherveille
229			`// generate burst counter`
230			`wire [3:0] burst_cnt_val;`
231			`assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;`
232			`assign burst_done = burst_cnt_val[3];`
233
234	19	rherveille	`always@(posedge clk_i)`
235	17	rherveille	`if ( (burst_done & vmem_ack) \| !vmem_acc)`
236			`case (ctrl_vbl) // synopsis full_case parallel_case`
237			`2'b00: burst_cnt <= #1 3'b000; // burst length 1`
238			`2'b01: burst_cnt <= #1 3'b001; // burst length 2`
239			`2'b10: burst_cnt <= #1 3'b011; // burst length 4`
240			`2'b11: burst_cnt <= #1 3'b111; // burst length 8`
241			`endcase`
242			`else if(vmem_ack)`
243			`burst_cnt <= #1 burst_cnt_val[2:0];`
244
245			`//`
246			`// generate image counters`
247			`//`
248
249			`// hgate counter`
250	19	rherveille	`reg [15:0] hgate_cnt;`
251			`reg [16:0] hgate_cnt_val;`
252			`reg [1:0] hgate_div_cnt;`
253			`reg [2:0] hgate_div_val;`
254	17	rherveille
255	19	rherveille	`wire hdone = hgate_cnt_val[16] & vmem_ack; // ????`
256
257			`always@(hgate_cnt or hgate_div_cnt or ctrl_cd)`
258			`begin`
259			`hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;`
260
261			`if (ctrl_cd != 2'b10)`
262			`hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;`
263			`else if ( hgate_div_val[2] )`
264			`hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;`
265	17	rherveille	`else`
266	19	rherveille	`hgate_cnt_val = {1'b0, hgate_cnt};`
267			`end`
268	17	rherveille
269	19	rherveille	`always@(posedge clk_i)`
270			`if (sclr)`
271			`begin`
272			`case(ctrl_cd) // synopsys full_case parallel_case`
273			`2'b00: // 8bpp`
274			`hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle`
275			`2'b01: //16bpp`
276			`hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle`
277			`2'b10: //24bpp`
278			`hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle`
279	28	rherveille	`2'b11: //32bpp`
280			`hgate_cnt <= #1 Thgate; // 1 pixel per cycle`
281	19	rherveille	`endcase`
282
283			`hgate_div_cnt <= 2'b10;`
284			`end`
285			`else if (vmem_ack)`
286			`if (hdone)`
287			`begin`
288			`case(ctrl_cd) // synopsys full_case parallel_case`
289			`2'b00: // 8bpp`
290			`hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle`
291			`2'b01: //16bpp`
292			`hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle`
293			`2'b10: //24bpp`
294			`hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle`
295	28	rherveille	`2'b11: //32bpp`
296			`hgate_cnt <= #1 Thgate; // 1 pixel per cycle`
297	19	rherveille	`endcase`
298			`hgate_div_cnt <= #1 2'b10;`
299			`end`
300			`else //if (vmem_ack)`
301			`begin`
302			`hgate_cnt <= #1 hgate_cnt_val[15:0];`
303
304			`if ( hgate_div_val[2] )`
305			`hgate_div_cnt <= #1 2'b10;`
306			`else`
307			`hgate_div_cnt <= #1 hgate_div_val[1:0];`
308			`end`
309
310	17	rherveille	`// vgate counter`
311	19	rherveille	`reg [15:0] vgate_cnt;`
312			`wire [16:0] vgate_cnt_val = {1'b0, vgate_cnt} -17'h1;`
313			`wire vdone = vgate_cnt_val[16];`
314	17	rherveille
315	19	rherveille	`always@(posedge clk_i)`
316			`if (sclr)`
317	17	rherveille	`vgate_cnt <= #1 Tvgate;`
318	19	rherveille	`else if (ImDoneStrb)`
319			`vgate_cnt <= #1 Tvgate;`
320			`else if (hdone)`
321			`vgate_cnt <= #1 vgate_cnt_val[15:0];`
322	17	rherveille
323	30	rherveille	`assign ImDone = hdone & vdone;`
324	19	rherveille
325	17	rherveille	`assign ImDoneStrb = ImDone & !dImDone;`
326
327	19	rherveille	`always@(posedge clk_i)`
328			`begin`
329	17	rherveille	`dImDone <= #1 ImDone;`
330	19	rherveille	`dImDoneStrb <= #1 ImDoneStrb;`
331			`end`
332	17	rherveille
333			`//`
334			`// generate addresses`
335			`//`
336
337			`// select video memory base address`
338	19	rherveille	`always@(posedge clk_i)`
339			`if (dImDoneStrb \| sclr)`
340	17	rherveille	`if (!sel_VBA)`
341			`vmemA <= #1 VBAa;`
342			`else`
343			`vmemA <= #1 VBAb;`
344			`else if (vmem_ack)`
345			`vmemA <= #1 vmemA +30'h1;`
346
347			`// generate wishbone signals`
348	19	rherveille	`assign adr_o = {vmemA, 2'b00};`
349			`wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone;`
350	17	rherveille
351	19	rherveille	`always@(posedge clk_i or negedge nrst_i)`
352			`if (!nrst_i)`
353	17	rherveille	`begin`
354	19	rherveille	`cyc_o <= #1 1'b0;`
355			`stb_o <= #1 1'b0;`
356			`sel_o <= #1 4'b1111;`
357			`cab_o <= #1 1'b0;`
358			`we_o <= #1 1'b0;`
359	17	rherveille	`end`
360			`else`
361	19	rherveille	`if (rst_i)`
362	17	rherveille	`begin`
363	19	rherveille	`cyc_o <= #1 1'b0;`
364			`stb_o <= #1 1'b0;`
365			`sel_o <= #1 4'b1111;`
366			`cab_o <= #1 1'b0;`
367			`we_o <= #1 1'b0;`
368	17	rherveille	`end`
369			`else`
370			`begin`
371	19	rherveille	`cyc_o <= #1 wb_cycle;`
372			`stb_o <= #1 wb_cycle;`
373			`sel_o <= #1 4'b1111; // only 32bit accesses are supported`
374			`cab_o <= #1 wb_cycle;`
375			`we_o <= #1 1'b0; // read only`
376	17	rherveille	`end`
377
378	30	rherveille	`// video-data buffer (temporary store data read from video memory)`
379	19	rherveille	`vga_fifo #(4, 32) data_fifo (`
380			`.clk(clk_i),`
381	17	rherveille	`.aclr(1'b1),`
382	19	rherveille	`.sclr(sclr),`
383			`.d(dat_i),`
384	17	rherveille	`.wreq(vmem_ack),`
385	19	rherveille	`.q(data_fifo_q),`
386			`.rreq(data_fifo_rreq),`
387			`.empty(data_fifo_empty),`
388			`.hfull(data_fifo_hfull),`
389	17	rherveille	`.full()`
390			`);`
391
392	19	rherveille	`assign nvmem_req = data_fifo_hfull;`
393	17	rherveille
394
395			`// hookup color processor`
396			`vga_colproc color_proc (`
397	19	rherveille	`.clk(clk_i),`
398			`.srst(sclr),`
399	30	rherveille	`.vdat_buffer_di(data_fifo_q),`
400	17	rherveille	`.ColorDepth(ctrl_cd),`
401			`.PseudoColor(ctrl_pc),`
402	30	rherveille	`.vdat_buffer_empty(data_fifo_empty),`
403			`.vdat_buffer_rreq(data_fifo_rreq),`
404			`.rgb_fifo_full(rgb_fifo_full),`
405			`.rgb_fifo_wreq(color_proc_wreq),`
406			`.r(color_proc_q[23:16]),`
407			`.g(color_proc_q[15:8]),`
408			`.b(color_proc_q[7:0]),`
409	17	rherveille	`.clut_req(clut_req),`
410	19	rherveille	`.clut_ack(clut_ack),`
411	17	rherveille	`.clut_offs(clut_offs),`
412	19	rherveille	`.clut_q(clut_q)`
413	17	rherveille	`);`
414
415	30	rherveille	`// hookup data-source-selector && hardware cursor module`
416			`ifdef VGA_HWC1
417			`reg scursor1_ld;`
418			`reg scursor1_en;`
419			`reg [31:0] scursor1_xy;`
420			`reg sddImDoneFifoQ, sdImDoneFifoQ;`
421
422			`always@(posedge clk_i)`
423			`if (ssel1_wreq)`
424			`begin`
425			`sdImDoneFifoQ <= #1 dImDoneFifoQ;`
426			`sddImDoneFifoQ <= #1 sdImDoneFifoQ;`
427			`end`
428
429			`always@(posedge clk_i)`
430			`if (sclr)`
431			`scursor1_ld <= #1 1'b0;`
432			`else`
433			`scursor1_ld <= #1 cursor1_ld \| (scursor1_ld & !(ddImDoneFifoQ & !dImDoneFifoQ));`
434
435			`always@(posedge clk_i)`
436			`if (sclr)`
437			`scursor1_en <= #1 1'b0;`
438			`else if (scursor1_ld)`
439			`scursor1_en <= #1 cursor1_en;`
440
441			`always@(posedge clk_i)`
442			`if (scursor1_ld)`
443			`scursor1_xy <= #1 cursor1_xy;`
444
445			`vga_ssel ssel_and_hw_cursor1 (`
446			`.clk(clk_i),`
447			`.rst_i(sclr),`
448			`.Thgate(Thgate),`
449			`.Tvgate(Tvgate),`
450			`.idat(color_proc_q),`
451			`.idat_wreq(color_proc_wreq),`
452			`.cursor_xy(scursor1_xy),`
453			`.cursor_en(scursor1_en),`
454			`.cursor_adr(cursor_adr),`
455			`.cursor_we(cursor1_we),`
456			`.cursor_dat(dat_i),`
457			`.rgb_fifo_wreq(ssel1_wreq),`
458			`.rgb(ssel1_q)`
459			`);`
460			`else
461			`wire sddImDoneFifoQ, sdImDoneFifoQ;`
462
463			`assign ssel1_wreq = color_proc_wreq;`
464			`assign ssel1_q = color_proc_q;`
465
466			`assign sdImDoneFifoQ = dImDoneFifoQ;`
467			`assign sddImDoneFifoQ = ddImDoneFifoQ;`
468			`endif
469
470			`ifdef VGA_HWC0
471			`reg scursor0_ld;`
472			`reg scursor0_en;`
473			`reg [31:0] scursor0_xy;`
474
475			`always@(posedge clk_i)`
476			`if (sclr)`
477			`scursor0_ld <= #1 1'b0;`
478			`else`
479			`scursor0_ld <= #1 cursor0_ld \| (scursor0_ld & !(sddImDoneFifoQ & !sdImDoneFifoQ));`
480
481			`always@(posedge clk_i)`
482			`if (sclr)`
483			`scursor0_en <= #1 1'b0;`
484			`else if (scursor0_ld)`
485			`scursor0_en <= #1 cursor0_en;`
486
487			`always@(posedge clk_i)`
488			`if (scursor0_ld)`
489			`scursor0_xy <= #1 cursor0_xy;`
490
491			`vga_ssel ssel_and_hw_cursor0 (`
492			`.clk(clk_i),`
493			`.rst_i(sclr),`
494			`.Thgate(Thgate),`
495			`.Tvgate(Tvgate),`
496			`.idat(ssel1_q),`
497			`.idat_wreq(ssel1_wreq),`
498			`.cursor_xy(scursor0_xy),`
499			`.cursor_en(scursor0_en),`
500			`.cursor_adr(cursor_adr),`

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_wb_master.v] - Blame information for rev 30