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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant enhanced VGA/LCD Core            ////
////  Wishbone master interface                                  ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/vga_lcd ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_wb_master.v,v 1.13 2003-03-19 12:50:45 rherveille Exp $
//
//  $Date: 2003-03-19 12:50:45 $
//  $Revision: 1.13 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.12  2003/03/18 21:45:48  rherveille
//               Added WISHBONE revB.3 Registered Feedback Cycles support
//
//               Revision 1.11  2002/04/20 10:02:39  rherveille
//               Changed video timing generator.
//               Changed wishbone master vertical gate count code.
//               Fixed a potential bug in the wishbone slave (cursor color register readout).
//
//               Revision 1.10  2002/03/28 04:59:25  rherveille
//               Fixed two small bugs that only showed up when the hardware cursors were disabled
//
//               Revision 1.9  2002/03/04 16:05:52  rherveille
//               Added hardware cursor support to wishbone master.
//               Added provision to turn-off 3D cursors.
//               Fixed some minor bugs.
//
//               Revision 1.8  2002/03/04 11:01:59  rherveille
//               Added 64x64pixels 4bpp hardware cursor support.
//
//               Revision 1.7  2002/02/16 10:40:00  rherveille
//               Some minor bug-fixes.
//               Changed vga_ssel into vga_curproc (cursor processor).
//
//               Revision 1.6  2002/02/07 05:42:10  rherveille
//               Fixed some bugs discovered by modified testbench
//               Removed / Changed some strange logic constructions
//               Started work on hardware cursor support (not finished yet)
//               Changed top-level name to vga_enh_top.v
//
 
`include "timescale.v"
`include "vga_defines.v"
 
module vga_wb_master (clk_i, rst_i, nrst_i,
        cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
        ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw,
        cursor0_en, cursor0_res, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_o, cc0_dat_i,
        cursor1_en, cursor1_res, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_o, cc1_dat_i,
        VBAa, VBAb, Thgate, Tvgate,
        stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full,
        clut_req, clut_ack, clut_adr, clut_q);
 
        // inputs & outputs
 
        // wishbone signals
        input         clk_i;    // master clock input
        input         rst_i;    // synchronous active high reset
        input         nrst_i;   // asynchronous low reset
        output        cyc_o;    // cycle output
        reg cyc_o;
        output        stb_o;    // strobe ouput
        reg stb_o;
        output [ 3:0] cti_o;    // cycle type id
        reg [3:0] cti_o;
        output [ 1:0] bte_o;    // burst type extension
        reg [1:0] bte_o;
        output        we_o;     // write enable output
        reg we_o;
        output [31:0] adr_o;    // address output
        output [ 3:0] sel_o;    // byte select outputs (only 32bits accesses are supported)
        reg [3:0] sel_o;
        input         ack_i;    // wishbone cycle acknowledge 
        input         err_i;    // wishbone cycle error
        input [31:0]  dat_i;    // wishbone data in
 
        output        sint;     // non recoverable error, interrupt host
 
        // control register settings
        input       ctrl_ven;   // video enable bit
        input [1:0] ctrl_cd;    // color depth
        input       ctrl_pc;    // 8bpp pseudo color/bw
        input [1:0] ctrl_vbl;   // burst length
        input       ctrl_vbsw;  // enable video bank switching
        input       ctrl_cbsw;  // enable clut bank switching
 
        input          cursor0_en;  // enable hardware cursor0
        input          cursor0_res; // cursor0 resolution
        input  [31: 0] cursor0_xy;  // (x,y) address hardware cursor0
        input  [31:11] cursor0_ba;  // cursor0 video memory base address
        input          cursor0_ld;  // reload cursor0 from video memory
        output [ 3: 0] cc0_adr_o;   // cursor0 color registers address output
        input  [15: 0] cc0_dat_i;   // cursor0 color registers data input
        input          cursor1_en;  // enable hardware cursor1
        input          cursor1_res; // cursor1 resolution
        input  [31: 0] cursor1_xy;  // (x,y) address hardware cursor1
        input  [31:11] cursor1_ba;  // cursor1 video memory base address
        input          cursor1_ld;  // reload cursor1 from video memory
        output [ 3: 0] cc1_adr_o;   // cursor1 color registers address output
        input  [15: 0] cc1_dat_i;   // cursor1 color registers data input
 
        // video memory addresses
        input [31: 2] VBAa;     // video memory base address A
        input [31: 2] VBAb;     // video memory base address B
 
        input [15:0] Thgate;    // horizontal visible area (in pixels)
        input [15:0] Tvgate;    // vertical visible area (in horizontal lines)
 
        output stat_avmp;       // active video memory page
        output stat_acmp;       // active CLUT memory page
        reg stat_acmp;
        output vmem_switch;     // video memory bank-switch request: memory page switched (when enabled)
        output clut_switch;     // clut memory bank-switch request: clut page switched (when enabled)
 
        // to/from line-fifo
        output        line_fifo_wreq;
        output [23:0] line_fifo_d;
        input         line_fifo_full;
 
        // to/from color lookup-table
        output        clut_req;  // clut access request
        input         clut_ack;  // clut access acknowledge
        output [ 8:0] clut_adr;  // clut access address
        input  [23:0] clut_q;    // clut access data in
 
        //
        // variable declarations
        //
 
        reg vmem_acc;                 // video memory access
        wire vmem_req_n, vmem_ack;    // NOT video memory access request // video memory access acknowledge
 
        wire ImDone;                  // Done reading image from video mem 
        reg  dImDone;                 // delayed ImDone
        wire  ImDoneStrb;             // image done (strobe signal)
        reg  dImDoneStrb;             // delayed ImDoneStrb
 
        wire data_fifo_rreq, data_fifo_empty, data_fifo_hfull;
        wire [31:0] data_fifo_q;
        wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d;
        wire        color_proc_wreq, ssel1_wreq, rgb_fifo_wreq;
        wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq;
        wire ImDoneFifoQ;
        reg  dImDoneFifoQ, ddImDoneFifoQ;
 
        reg sclr; // synchronous clear
 
        wire [7:0] clut_offs; // color lookup table offset
 
        //
        // hardware cursors
        reg [31:11] cursor_ba;              // cursor pattern base address
        reg [ 8: 0] cursor_adr;             // cursor pattern offset
        wire        cursor0_we, cursor1_we; // cursor buffers write_request
        reg         ld_cursor0, ld_cursor1; // reload cursor0, cursor1
        reg         cur_acc;                // cursor processors request memory access
        reg         cur_acc_sel;            // which cursor to reload
        wire        cur_ack;                // cursor processor memory access acknowledge
        wire        cur_done;               // done reading cursor pattern
 
 
        //
        // module body
        //
 
        // generate synchronous clear
        always @(posedge clk_i)
          sclr <= #1 ~ctrl_ven;
 
        //
        // WISHBONE block
        //
        reg  [ 2:0] burst_cnt;                       // video memory burst access counter
        wire        burst_done;                      // completed burst access to video mem
        reg         sel_VBA;                         // select video memory base address
        reg  [31:2] vmemA;                           // video memory address
 
        // wishbone access controller, video memory access request has highest priority (try to keep fifo full)
        always @(posedge clk_i)
          if (sclr)
            vmem_acc <= #1 1'b0; // video memory access request
          else
            vmem_acc <= #1 (!vmem_req_n | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone & !cur_acc;
 
        always @(posedge clk_i)
          if (sclr)
            cur_acc <= #1 1'b0; // cursor processor memory access request
          else
            cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done;
 
 
        assign vmem_ack = ack_i & stb_o & vmem_acc;
        assign cur_ack  = ack_i & stb_o & cur_acc;
        assign sint = err_i; // Non recoverable error, interrupt host system
 
 
        // select active memory page
        assign vmem_switch = ImDoneStrb;
 
        always @(posedge clk_i)
          if (sclr)
            sel_VBA <= #1 1'b0;
          else if (ctrl_vbsw)
            sel_VBA <= #1 sel_VBA ^ vmem_switch;  // select next video memory bank when finished reading current bank (and bank switch enabled)
 
        assign stat_avmp = sel_VBA; // assign output
 
        // selecting active clut page / cursor data
        // delay image done same amount as video-memory data
        vga_fifo #(4, 1) clut_sw_fifo (
                .clk(clk_i),
                .aclr(1'b1),
                .sclr(sclr),
                .d(ImDone),
                .wreq(vmem_ack),
                .q(ImDoneFifoQ),
                .rreq(data_fifo_rreq),
                .empty(),
                .hfull(),
                .full()
        );
 
        //
        // clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay
        always @(posedge clk_i)
          if (sclr)
            dImDoneFifoQ <= #1 1'b0;
          else if (data_fifo_rreq)
            dImDoneFifoQ <= #1 ImDoneFifoQ;
 
        always @(posedge clk_i)
          if (sclr)
            ddImDoneFifoQ <= #1 1'b0;
          else
            ddImDoneFifoQ <= #1 dImDoneFifoQ;
 
        assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ;
 
        always @(posedge clk_i)
          if (sclr)
            stat_acmp <= #1 1'b0;
          else if (ctrl_cbsw)
            stat_acmp <= #1 stat_acmp ^ clut_switch;  // select next clut when finished reading clut for current video bank (and bank switch enabled)
 
        //
        // generate clut-address
        assign clut_adr = {stat_acmp, clut_offs};
 
        //
        // generate burst counter
        wire [3:0] burst_cnt_val;
        assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
        assign burst_done = burst_cnt_val[3];
 
        always @(posedge clk_i)
          if ( (burst_done & vmem_ack) | !vmem_acc)
            case (ctrl_vbl) // synopsis full_case parallel_case
              2'b00: burst_cnt <= #1 3'b000; // burst length 1
              2'b01: burst_cnt <= #1 3'b001; // burst length 2
              2'b10: burst_cnt <= #1 3'b011; // burst length 4
              2'b11: burst_cnt <= #1 3'b111; // burst length 8
            endcase
          else if(vmem_ack)
            burst_cnt <= #1 burst_cnt_val[2:0];
 
        //
        // generate image counters
        //
 
        // hgate counter
        reg  [15:0] hgate_cnt;
        reg  [16:0] hgate_cnt_val;
        reg  [1:0]  hgate_div_cnt;
        reg  [2:0]  hgate_div_val;
 
        wire hdone = hgate_cnt_val[16] & vmem_ack; // ????
 
        always @(hgate_cnt or hgate_div_cnt or ctrl_cd)
          begin
              hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;
 
              if (ctrl_cd != 2'b10)
                hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
              else if ( hgate_div_val[2] )
                hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
              else
                hgate_cnt_val = {1'b0, hgate_cnt};
          end
 
        always @(posedge clk_i)
          if (sclr)
            begin
                case(ctrl_cd) // synopsys full_case parallel_case
                  2'b00: hgate_cnt <= #1 Thgate >> 2; //  8bpp, 4 pixels per cycle
                  2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle
                  2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle
                  2'b11: hgate_cnt <= #1 Thgate;      // 32bpp, 1 pixel per cycle
                endcase
 
                hgate_div_cnt <= 2'b10;
            end
          else if (vmem_ack)
            if (hdone)
              begin
                  case(ctrl_cd) // synopsys full_case parallel_case
                    2'b00: hgate_cnt <= #1 Thgate >> 2; //  8bpp, 4 pixels per cycle
                    2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle
                    2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle
                    2'b11: hgate_cnt <= #1 Thgate;      // 32bpp, 1 pixel per cycle
                  endcase
 
                  hgate_div_cnt <= 2'b10;
              end
            else //if (vmem_ack)
              begin
                  hgate_cnt <= #1 hgate_cnt_val[15:0];
 
                  if ( hgate_div_val[2] )
                    hgate_div_cnt <= #1 2'b10;
                  else
                    hgate_div_cnt <= #1 hgate_div_val[1:0];
              end
 
        // vgate counter
        reg  [15:0] vgate_cnt;
        wire [16:0] vgate_cnt_val;
        wire        vdone;
 
        assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;
        assign vdone = vgate_cnt_val[16];
 
        always @(posedge clk_i)
          if (sclr || ImDoneStrb)
            vgate_cnt <= #1 Tvgate;
          else if (hdone)
            vgate_cnt <= #1 vgate_cnt_val[15:0];
 
        assign ImDone = hdone & vdone;
 
        assign ImDoneStrb = ImDone & !dImDone;
 
        always @(posedge clk_i)
          begin
              dImDone <= #1 ImDone;
              dImDoneStrb <= #1 ImDoneStrb;
          end
 
        //
        // generate addresses
        //
 
        // select video memory base address
        always @(posedge clk_i)
          if (dImDoneStrb | sclr)
            if (!sel_VBA)
              vmemA <= #1 VBAa;
            else
              vmemA <= #1 VBAb;
          else if (vmem_ack)
            vmemA <= #1 vmemA +30'h1;
 
 
        ////////////////////////////////////
        // hardware cursor signals section
        //
        always @(posedge clk_i)
          if (ImDone)
            cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority
 
        always @(posedge clk_i)
        if (sclr)
          begin
              ld_cursor0 <= #1 1'b0;
              ld_cursor1 <= #1 1'b0;
          end
        else
          begin
              ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done &  cur_acc_sel));
              ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel));
          end
 
        // select cursor base address
        always @(posedge clk_i)
          if (!cur_acc)
            cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba;
 
        // generate pattern offset
        wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1;
        assign cur_done = next_cursor_adr[9] & cur_ack;
 
        always @(posedge clk_i)
          if (!cur_acc)
            cursor_adr <= #1 9'h0;
          else if (cur_ack)
            cursor_adr <= #1 next_cursor_adr;
 
        // generate cursor buffers write enable signals
        assign cursor1_we = cur_ack & !cur_acc_sel;
        assign cursor0_we = cur_ack &  cur_acc_sel;
 
 
        //////////////////////////////
        // generate wishbone signals
        //
        assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};
        wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & vmem_req_n) & !ImDone ||
                        cur_acc & !cur_done;
 
        wire [2:0] cti_vid = (burst_cnt == 3'h1)   ? 3'b111 : 3'b010;
        wire [2:0] cti_cur = &next_cursor_adr[8:0] ? 3'b111 : 3'b010;
        reg  [2:0] cti;
        always @(ctrl_vbl or cur_acc or cti_cur or cti_vid)
          case (ctrl_vbl)
            3'b000:  cti <= #1 3'b000; // wishbone classic cycle
 
            default: cti <= #1 cur_acc ? cti_cur : cti_vid;
          endcase
 
        always @(posedge clk_i or negedge nrst_i)
          if (!nrst_i)
            begin
                cyc_o <= #1 1'b0;
                stb_o <= #1 1'b0;
                sel_o <= #1 4'b1111;
                cti_o <= #1 3'b000;
                bte_o <= #1 2'b00;
                we_o  <= #1 1'b0;
            end
          else
            if (rst_i)
              begin
                  cyc_o <= #1 1'b0;
                  stb_o <= #1 1'b0;
                  sel_o <= #1 4'b1111;
                  cti_o <= #1 3'b000;
                  bte_o <= #1 2'b00;
                  we_o  <= #1 1'b0;
              end
            else
              begin
                  cyc_o <= #1 wb_cycle;
                  stb_o <= #1 wb_cycle;
                  sel_o <= #1 4'b1111;   // only 32bit accesses are supported
                  we_o  <= #1 1'b0;      // read only
 
                  if (vmem_ack | cur_ack)
                    cti_o <= #1 cti;     // cycle type
 
                  bte_o <= #1 2'b00;     // linear burst
              end
 
        //
        // video-data buffer (temporary store data read from video memory)
        vga_fifo #(4, 32) data_fifo (
                .clk(clk_i),
                .aclr(1'b1),
                .sclr(sclr),
                .d(dat_i),
                .wreq(vmem_ack),
                .q(data_fifo_q),
                .rreq(data_fifo_rreq),
                .empty(data_fifo_empty),
                .hfull(data_fifo_hfull),
                .full()
        );
 
        assign vmem_req_n = data_fifo_hfull;
 
        //
        // hookup color processor
        vga_colproc color_proc (
                .clk(clk_i),
                .srst(sclr),
                .vdat_buffer_di(data_fifo_q),
                .ColorDepth(ctrl_cd),
                .PseudoColor(ctrl_pc),
                .vdat_buffer_empty(data_fifo_empty),
                .vdat_buffer_rreq(data_fifo_rreq),
                .rgb_fifo_full(rgb_fifo_full),
                .rgb_fifo_wreq(color_proc_wreq),
                .r(color_proc_q[23:16]),
                .g(color_proc_q[15:8]),
                .b(color_proc_q[7:0]),
                .clut_req(clut_req),
                .clut_ack(clut_ack),
                .clut_offs(clut_offs),
                .clut_q(clut_q)
        );
 
        //
        // hookup data-source-selector && hardware cursor module
`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled)
        wire cursor1_ld_strb;
        reg scursor1_en;
        reg scursor1_res;
        reg [31:0] scursor1_xy;
 
        assign cursor1_ld_strb = ddImDoneFifoQ & !dImDoneFifoQ;
 
        always @(posedge clk_i)
          if (sclr)
            scursor1_en <= #1 1'b0;
          else if (cursor1_ld_strb)
            scursor1_en <= #1 cursor1_en;
 
        always @(posedge clk_i)
          if (cursor1_ld_strb)
            scursor1_xy <= #1 cursor1_xy;
 
        always @(posedge clk_i)
          if (cursor1_ld_strb)
            scursor1_res <= #1 cursor1_res;
 
        vga_curproc hw_cursor1 (
                .clk(clk_i),
                .rst_i(sclr),
                .Thgate(Thgate),
                .Tvgate(Tvgate),
                .idat(color_proc_q),
                .idat_wreq(color_proc_wreq),
                .cursor_xy(scursor1_xy),
                .cursor_res(scursor1_res),
                .cursor_en(scursor1_en),
                .cursor_wadr(cursor_adr),
                .cursor_we(cursor1_we),
                .cursor_wdat(dat_i),
                .cc_adr_o(cc1_adr_o),
                .cc_dat_i(cc1_dat_i),
                .rgb_fifo_wreq(ssel1_wreq),
                .rgb(ssel1_q)
        );
 
`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
        reg sddImDoneFifoQ, sdImDoneFifoQ;
 
        always @(posedge clk_i)
          if (ssel1_wreq)
            begin
                sdImDoneFifoQ  <= #1 dImDoneFifoQ;
                sddImDoneFifoQ <= #1 sdImDoneFifoQ;
            end
`endif
 
`else           // Hardware Cursor1 disabled, generate pass-through signals
        assign ssel1_wreq = color_proc_wreq;
        assign ssel1_q    = color_proc_q;
 
        assign cc1_adr_o  = 4'h0;
 
`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
        wire sddImDoneFifoQ, sdImDoneFifoQ;
 
        assign sdImDoneFifoQ  = dImDoneFifoQ;
        assign sddImDoneFifoQ = ddImDoneFifoQ;
`endif
 
`endif
 
 
`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled)
        wire cursor0_ld_strb;
        reg scursor0_en;
        reg scursor0_res;
        reg [31:0] scursor0_xy;
 
        assign cursor0_ld_strb = sddImDoneFifoQ & !sdImDoneFifoQ;
 
        always @(posedge clk_i)
          if (sclr)
            scursor0_en <= #1 1'b0;
          else if (cursor0_ld_strb)
            scursor0_en <= #1 cursor0_en;
 
        always @(posedge clk_i)
          if (cursor0_ld_strb)
            scursor0_xy <= #1 cursor0_xy;
 
        always @(posedge clk_i)
          if (cursor0_ld_strb)
            scursor0_res <= #1 cursor0_res;
 
        vga_curproc hw_cursor0 (
                .clk(clk_i),
                .rst_i(sclr),
                .Thgate(Thgate),
                .Tvgate(Tvgate),
                .idat(ssel1_q),
                .idat_wreq(ssel1_wreq),
                .cursor_xy(scursor0_xy),
                .cursor_en(scursor0_en),
                .cursor_res(scursor0_res),
                .cursor_wadr(cursor_adr),
                .cursor_we(cursor0_we),
                .cursor_wdat(dat_i),
                .cc_adr_o(cc0_adr_o),
                .cc_dat_i(cc0_dat_i),
                .rgb_fifo_wreq(rgb_fifo_wreq),
                .rgb(rgb_fifo_d)
        );
`else   // Hardware Cursor0 disabled, generate pass-through signals
        assign rgb_fifo_wreq = ssel1_wreq;
        assign rgb_fifo_d = ssel1_q;
 
        assign cc0_adr_o  = 4'h0;
`endif
 
        //
        // hookup RGB buffer (temporary station between WISHBONE-clock-domain
        // and pixel-clock-domain)
        // The cursor_processor pipelines introduce a delay between the color
        // processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate
        // for this we double the rgb_fifo.
        vga_fifo #(4, 24) rgb_fifo (
                .clk(clk_i),
                .aclr(1'b1),
                .sclr(sclr),
                .d(rgb_fifo_d),
                .wreq(rgb_fifo_wreq),
                .q(line_fifo_d),
                .rreq(rgb_fifo_rreq),
                .empty(rgb_fifo_empty),
                .hfull(rgb_fifo_full),
                .full()
        );
 
        assign rgb_fifo_rreq = !line_fifo_full && !rgb_fifo_empty;
        assign line_fifo_wreq = rgb_fifo_rreq;
 
endmodule

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	30	rherveille	`//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////`
4	23	rherveille	`//// Wishbone master interface ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	30	rherveille	`//// Copyright (C) 2001, 2002 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16	23	rherveille	`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	17	rherveille	`//`
40	45	rherveille	`// $Id: vga_wb_master.v,v 1.13 2003-03-19 12:50:45 rherveille Exp $`
41	17	rherveille	`//`
42	45	rherveille	`// $Date: 2003-03-19 12:50:45 $`
43			`// $Revision: 1.13 $`
44	23	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	45	rherveille	`// Revision 1.12 2003/03/18 21:45:48 rherveille`
51			`// Added WISHBONE revB.3 Registered Feedback Cycles support`
52			`//`
53	43	rherveille	`// Revision 1.11 2002/04/20 10:02:39 rherveille`
54			`// Changed video timing generator.`
55			`// Changed wishbone master vertical gate count code.`
56			`// Fixed a potential bug in the wishbone slave (cursor color register readout).`
57			`//`
58	39	rherveille	`// Revision 1.10 2002/03/28 04:59:25 rherveille`
59			`// Fixed two small bugs that only showed up when the hardware cursors were disabled`
60			`//`
61	36	rherveille	`// Revision 1.9 2002/03/04 16:05:52 rherveille`
62			`// Added hardware cursor support to wishbone master.`
63			`// Added provision to turn-off 3D cursors.`
64			`// Fixed some minor bugs.`
65			`//`
66	34	rherveille	`// Revision 1.8 2002/03/04 11:01:59 rherveille`
67			`// Added 64x64pixels 4bpp hardware cursor support.`
68			`//`
69	33	rherveille	`// Revision 1.7 2002/02/16 10:40:00 rherveille`
70			`// Some minor bug-fixes.`
71			`// Changed vga_ssel into vga_curproc (cursor processor).`
72			`//`
73	31	rherveille	`// Revision 1.6 2002/02/07 05:42:10 rherveille`
74			`// Fixed some bugs discovered by modified testbench`
75			`// Removed / Changed some strange logic constructions`
76			`// Started work on hardware cursor support (not finished yet)`
77			`// Changed top-level name to vga_enh_top.v`
78			`//`
79	17	rherveille
80			`include "timescale.v"
81	30	rherveille	`include "vga_defines.v"
82	17	rherveille
83	43	rherveille	`module vga_wb_master (clk_i, rst_i, nrst_i,`
84			`cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,`
85	30	rherveille	`ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw,`
86	33	rherveille	`cursor0_en, cursor0_res, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_o, cc0_dat_i,`
87			`cursor1_en, cursor1_res, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_o, cc1_dat_i,`
88	30	rherveille	`VBAa, VBAb, Thgate, Tvgate,`
89	19	rherveille	`stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full,`
90			`clut_req, clut_ack, clut_adr, clut_q);`
91	17	rherveille
92			`// inputs & outputs`
93
94			`// wishbone signals`
95	19	rherveille	`input clk_i; // master clock input`
96			`input rst_i; // synchronous active high reset`
97			`input nrst_i; // asynchronous low reset`
98			`output cyc_o; // cycle output`
99			`reg cyc_o;`
100			`output stb_o; // strobe ouput`
101			`reg stb_o;`
102	43	rherveille	`output [ 3:0] cti_o; // cycle type id`
103			`reg [3:0] cti_o;`
104			`output [ 1:0] bte_o; // burst type extension`
105			`reg [1:0] bte_o;`
106	19	rherveille	`output we_o; // write enable output`
107			`reg we_o;`
108			`output [31:0] adr_o; // address output`
109			`output [ 3:0] sel_o; // byte select outputs (only 32bits accesses are supported)`
110			`reg [3:0] sel_o;`
111			`input ack_i; // wishbone cycle acknowledge`
112			`input err_i; // wishbone cycle error`
113			`input [31:0] dat_i; // wishbone data in`
114	17	rherveille
115	19	rherveille	`output sint; // non recoverable error, interrupt host`
116	17	rherveille
117			`// control register settings`
118			`input ctrl_ven; // video enable bit`
119			`input [1:0] ctrl_cd; // color depth`
120			`input ctrl_pc; // 8bpp pseudo color/bw`
121			`input [1:0] ctrl_vbl; // burst length`
122			`input ctrl_vbsw; // enable video bank switching`
123			`input ctrl_cbsw; // enable clut bank switching`
124
125	33	rherveille	`input cursor0_en; // enable hardware cursor0`
126			`input cursor0_res; // cursor0 resolution`
127			`input [31: 0] cursor0_xy; // (x,y) address hardware cursor0`
128			`input [31:11] cursor0_ba; // cursor0 video memory base address`
129			`input cursor0_ld; // reload cursor0 from video memory`
130			`output [ 3: 0] cc0_adr_o; // cursor0 color registers address output`
131			`input [15: 0] cc0_dat_i; // cursor0 color registers data input`
132			`input cursor1_en; // enable hardware cursor1`
133			`input cursor1_res; // cursor1 resolution`
134			`input [31: 0] cursor1_xy; // (x,y) address hardware cursor1`
135			`input [31:11] cursor1_ba; // cursor1 video memory base address`
136			`input cursor1_ld; // reload cursor1 from video memory`
137			`output [ 3: 0] cc1_adr_o; // cursor1 color registers address output`
138			`input [15: 0] cc1_dat_i; // cursor1 color registers data input`
139	30	rherveille
140	17	rherveille	`// video memory addresses`
141			`input [31: 2] VBAa; // video memory base address A`
142			`input [31: 2] VBAb; // video memory base address B`
143
144			`input [15:0] Thgate; // horizontal visible area (in pixels)`
145			`input [15:0] Tvgate; // vertical visible area (in horizontal lines)`
146
147			`output stat_avmp; // active video memory page`
148			`output stat_acmp; // active CLUT memory page`
149	19	rherveille	`reg stat_acmp;`
150			`output vmem_switch; // video memory bank-switch request: memory page switched (when enabled)`
151			`output clut_switch; // clut memory bank-switch request: clut page switched (when enabled)`
152	17	rherveille
153			`// to/from line-fifo`
154			`output line_fifo_wreq;`
155			`output [23:0] line_fifo_d;`
156			`input line_fifo_full;`
157
158	19	rherveille	`// to/from color lookup-table`
159			`output clut_req; // clut access request`
160			`input clut_ack; // clut access acknowledge`
161			`output [ 8:0] clut_adr; // clut access address`
162			`input [23:0] clut_q; // clut access data in`
163
164	17	rherveille	`//`
165			`// variable declarations`
166			`//`
167	19	rherveille
168			`reg vmem_acc; // video memory access`
169	43	rherveille	`wire vmem_req_n, vmem_ack; // NOT video memory access request // video memory access acknowledge`
170	17	rherveille
171	30	rherveille	`wire ImDone; // Done reading image from video mem`
172	19	rherveille	`reg dImDone; // delayed ImDone`
173			`wire ImDoneStrb; // image done (strobe signal)`
174			`reg dImDoneStrb; // delayed ImDoneStrb`
175
176			`wire data_fifo_rreq, data_fifo_empty, data_fifo_hfull;`
177			`wire [31:0] data_fifo_q;`
178	30	rherveille	`wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d;`
179			`wire color_proc_wreq, ssel1_wreq, rgb_fifo_wreq;`
180			`wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq;`
181	19	rherveille	`wire ImDoneFifoQ;`
182	30	rherveille	`reg dImDoneFifoQ, ddImDoneFifoQ;`
183	19	rherveille
184			`reg sclr; // synchronous clear`
185
186			`wire [7:0] clut_offs; // color lookup table offset`
187
188	34	rherveille	`//`
189			`// hardware cursors`
190			`reg [31:11] cursor_ba; // cursor pattern base address`
191			`reg [ 8: 0] cursor_adr; // cursor pattern offset`
192			`wire cursor0_we, cursor1_we; // cursor buffers write_request`
193			`reg ld_cursor0, ld_cursor1; // reload cursor0, cursor1`
194			`reg cur_acc; // cursor processors request memory access`
195			`reg cur_acc_sel; // which cursor to reload`
196			`wire cur_ack; // cursor processor memory access acknowledge`
197			`wire cur_done; // done reading cursor pattern`
198	30	rherveille
199	34	rherveille
200	17	rherveille	`//`
201			`// module body`
202			`//`
203
204	19	rherveille	`// generate synchronous clear`
205	43	rherveille	`always @(posedge clk_i)`
206			`sclr <= #1 ~ctrl_ven;`
207	17	rherveille
208			`//`
209			`// WISHBONE block`
210			`//`
211			`reg [ 2:0] burst_cnt; // video memory burst access counter`
212			`wire burst_done; // completed burst access to video mem`
213	19	rherveille	`reg sel_VBA; // select video memory base address`
214	43	rherveille	`reg [31:2] vmemA; // video memory address`
215	17	rherveille
216			`// wishbone access controller, video memory access request has highest priority (try to keep fifo full)`
217	43	rherveille	`always @(posedge clk_i)`
218			`if (sclr)`
219			`vmem_acc <= #1 1'b0; // video memory access request`
220			`else`
221			`vmem_acc <= #1 (!vmem_req_n \| (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone & !cur_acc;`
222	17	rherveille
223	43	rherveille	`always @(posedge clk_i)`
224			`if (sclr)`
225			`cur_acc <= #1 1'b0; // cursor processor memory access request`
226			`else`
227			`cur_acc <= #1 (cur_acc \| ImDone & (ld_cursor0 \| ld_cursor1)) & !cur_done;`
228	34	rherveille
229
230	43	rherveille	`assign vmem_ack = ack_i & stb_o & vmem_acc;`
231			`assign cur_ack = ack_i & stb_o & cur_acc;`
232	19	rherveille	`assign sint = err_i; // Non recoverable error, interrupt host system`
233	17	rherveille
234	34	rherveille
235	19	rherveille	`// select active memory page`
236			`assign vmem_switch = ImDoneStrb;`
237	17	rherveille
238	43	rherveille	`always @(posedge clk_i)`
239			`if (sclr)`
240			`sel_VBA <= #1 1'b0;`
241			`else if (ctrl_vbsw)`
242			`sel_VBA <= #1 sel_VBA ^ vmem_switch; // select next video memory bank when finished reading current bank (and bank switch enabled)`
243	17	rherveille
244			`assign stat_avmp = sel_VBA; // assign output`
245
246	30	rherveille	`// selecting active clut page / cursor data`
247			`// delay image done same amount as video-memory data`
248	19	rherveille	`vga_fifo #(4, 1) clut_sw_fifo (`
249			`.clk(clk_i),`
250			`.aclr(1'b1),`
251			`.sclr(sclr),`
252			`.d(ImDone),`
253	30	rherveille	`.wreq(vmem_ack),`
254	19	rherveille	`.q(ImDoneFifoQ),`
255			`.rreq(data_fifo_rreq),`
256			`.empty(),`
257			`.hfull(),`
258			`.full()`
259			`);`
260
261	34	rherveille	`//`
262	30	rherveille	`// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay`
263	43	rherveille	`always @(posedge clk_i)`
264			`if (sclr)`
265			`dImDoneFifoQ <= #1 1'b0;`
266			`else if (data_fifo_rreq)`
267			`dImDoneFifoQ <= #1 ImDoneFifoQ;`
268	19	rherveille
269	43	rherveille	`always @(posedge clk_i)`
270			`if (sclr)`
271			`ddImDoneFifoQ <= #1 1'b0;`
272			`else`
273			`ddImDoneFifoQ <= #1 dImDoneFifoQ;`
274	19	rherveille
275	30	rherveille	`assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ;`
276	19	rherveille
277	43	rherveille	`always @(posedge clk_i)`
278			`if (sclr)`
279			`stat_acmp <= #1 1'b0;`
280			`else if (ctrl_cbsw)`
281			`stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled)`
282	17	rherveille
283	34	rherveille	`//`
284	19	rherveille	`// generate clut-address`
285			`assign clut_adr = {stat_acmp, clut_offs};`
286	17	rherveille
287	34	rherveille	`//`
288	17	rherveille	`// generate burst counter`
289			`wire [3:0] burst_cnt_val;`
290			`assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;`
291			`assign burst_done = burst_cnt_val[3];`
292
293	43	rherveille	`always @(posedge clk_i)`
294			`if ( (burst_done & vmem_ack) \| !vmem_acc)`
295			`case (ctrl_vbl) // synopsis full_case parallel_case`
296			`2'b00: burst_cnt <= #1 3'b000; // burst length 1`
297			`2'b01: burst_cnt <= #1 3'b001; // burst length 2`
298			`2'b10: burst_cnt <= #1 3'b011; // burst length 4`
299			`2'b11: burst_cnt <= #1 3'b111; // burst length 8`
300			`endcase`
301			`else if(vmem_ack)`
302			`burst_cnt <= #1 burst_cnt_val[2:0];`
303	17	rherveille
304			`//`
305			`// generate image counters`
306			`//`
307
308			`// hgate counter`
309	19	rherveille	`reg [15:0] hgate_cnt;`
310			`reg [16:0] hgate_cnt_val;`
311			`reg [1:0] hgate_div_cnt;`
312			`reg [2:0] hgate_div_val;`
313	17	rherveille
314	19	rherveille	`wire hdone = hgate_cnt_val[16] & vmem_ack; // ????`
315
316	43	rherveille	`always @(hgate_cnt or hgate_div_cnt or ctrl_cd)`
317			`begin`
318			`hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;`
319	17	rherveille
320	43	rherveille	`if (ctrl_cd != 2'b10)`
321			`hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;`
322			`else if ( hgate_div_val[2] )`
323			`hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;`
324			`else`
325			`hgate_cnt_val = {1'b0, hgate_cnt};`
326			`end`
327	19	rherveille
328	43	rherveille	`always @(posedge clk_i)`
329			`if (sclr)`
330			`begin`
331			`case(ctrl_cd) // synopsys full_case parallel_case`
332			`2'b00: hgate_cnt <= #1 Thgate >> 2; // 8bpp, 4 pixels per cycle`
333			`2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle`
334			`2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle`
335			`2'b11: hgate_cnt <= #1 Thgate; // 32bpp, 1 pixel per cycle`
336			`endcase`
337	19	rherveille
338	43	rherveille	`hgate_div_cnt <= 2'b10;`
339			`end`
340			`else if (vmem_ack)`
341			`if (hdone)`
342			`begin`
343			`case(ctrl_cd) // synopsys full_case parallel_case`
344			`2'b00: hgate_cnt <= #1 Thgate >> 2; // 8bpp, 4 pixels per cycle`
345			`2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle`
346			`2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle`
347			`2'b11: hgate_cnt <= #1 Thgate; // 32bpp, 1 pixel per cycle`
348			`endcase`
349	19	rherveille
350	43	rherveille	`hgate_div_cnt <= 2'b10;`
351			`end`
352			`else //if (vmem_ack)`
353			`begin`
354			`hgate_cnt <= #1 hgate_cnt_val[15:0];`
355
356			`if ( hgate_div_val[2] )`
357			`hgate_div_cnt <= #1 2'b10;`
358			`else`
359			`hgate_div_cnt <= #1 hgate_div_val[1:0];`
360			`end`
361
362	17	rherveille	`// vgate counter`
363	19	rherveille	`reg [15:0] vgate_cnt;`
364	45	rherveille	`wire [16:0] vgate_cnt_val;`
365			`wire vdone;`
366	17	rherveille
367	45	rherveille	`assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;`
368			`assign vdone = vgate_cnt_val[16];`
369
370	43	rherveille	`always @(posedge clk_i)`
371			`if (sclr \|\| ImDoneStrb)`
372			`vgate_cnt <= #1 Tvgate;`
373			`else if (hdone)`
374	45	rherveille	`vgate_cnt <= #1 vgate_cnt_val[15:0];`
375	17	rherveille
376	30	rherveille	`assign ImDone = hdone & vdone;`
377	19	rherveille
378	17	rherveille	`assign ImDoneStrb = ImDone & !dImDone;`
379
380	43	rherveille	`always @(posedge clk_i)`
381			`begin`
382			`dImDone <= #1 ImDone;`
383			`dImDoneStrb <= #1 ImDoneStrb;`
384			`end`
385	17	rherveille
386			`//`
387			`// generate addresses`
388			`//`
389
390			`// select video memory base address`
391	43	rherveille	`always @(posedge clk_i)`
392			`if (dImDoneStrb \| sclr)`
393			`if (!sel_VBA)`
394			`vmemA <= #1 VBAa;`
395			`else`
396			`vmemA <= #1 VBAb;`
397			`else if (vmem_ack)`
398			`vmemA <= #1 vmemA +30'h1;`
399	17	rherveille
400	34	rherveille
401			`////////////////////////////////////`
402			`// hardware cursor signals section`
403			`//`
404	43	rherveille	`always @(posedge clk_i)`
405			`if (ImDone)`
406			`cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority`
407	34	rherveille
408	43	rherveille	`always @(posedge clk_i)`
409	34	rherveille	`if (sclr)`
410	43	rherveille	`begin`
411			`ld_cursor0 <= #1 1'b0;`
412			`ld_cursor1 <= #1 1'b0;`
413			`end`
414	34	rherveille	`else`
415	43	rherveille	`begin`
416			`ld_cursor0 <= #1 cursor0_ld \| (ld_cursor0 & !(cur_done & cur_acc_sel));`
417			`ld_cursor1 <= #1 cursor1_ld \| (ld_cursor1 & !(cur_done & !cur_acc_sel));`
418			`end`
419	34	rherveille
420			`// select cursor base address`
421	43	rherveille	`always @(posedge clk_i)`
422			`if (!cur_acc)`
423			`cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba;`
424	34	rherveille
425			`// generate pattern offset`
426			`wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1;`
427	43	rherveille	`assign cur_done = next_cursor_adr[9] & cur_ack;`
428	34	rherveille
429	43	rherveille	`always @(posedge clk_i)`
430			`if (!cur_acc)`
431			`cursor_adr <= #1 9'h0;`
432			`else if (cur_ack)`
433			`cursor_adr <= #1 next_cursor_adr;`
434	34	rherveille
435			`// generate cursor buffers write enable signals`
436			`assign cursor1_we = cur_ack & !cur_acc_sel;`
437			`assign cursor0_we = cur_ack & cur_acc_sel;`
438
439
440			`//////////////////////////////`
441	17	rherveille	`// generate wishbone signals`
442	34	rherveille	`//`
443			`assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};`
444	43	rherveille	`wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & vmem_req_n) & !ImDone \|\|`
445	34	rherveille	`cur_acc & !cur_done;`
446	17	rherveille
447	43	rherveille	`wire [2:0] cti_vid = (burst_cnt == 3'h1) ? 3'b111 : 3'b010;`
448			`wire [2:0] cti_cur = &next_cursor_adr[8:0] ? 3'b111 : 3'b010;`
449			`reg [2:0] cti;`
450			`always @(ctrl_vbl or cur_acc or cti_cur or cti_vid)`
451			`case (ctrl_vbl)`
452			`3'b000: cti <= #1 3'b000; // wishbone classic cycle`
453	17	rherveille
454	43	rherveille	`default: cti <= #1 cur_acc ? cti_cur : cti_vid;`
455			`endcase`
456
457			`always @(posedge clk_i or negedge nrst_i)`
458			`if (!nrst_i)`
459			`begin`
460			`cyc_o <= #1 1'b0;`
461			`stb_o <= #1 1'b0;`
462			`sel_o <= #1 4'b1111;`
463			`cti_o <= #1 3'b000;`
464			`bte_o <= #1 2'b00;`
465			`we_o <= #1 1'b0;`
466			`end`
467			`else`
468			`if (rst_i)`
469			`begin`
470			`cyc_o <= #1 1'b0;`
471			`stb_o <= #1 1'b0;`
472			`sel_o <= #1 4'b1111;`
473			`cti_o <= #1 3'b000;`
474			`bte_o <= #1 2'b00;`
475			`we_o <= #1 1'b0;`
476			`end`
477			`else`
478			`begin`
479			`cyc_o <= #1 wb_cycle;`
480			`stb_o <= #1 wb_cycle;`
481			`sel_o <= #1 4'b1111; // only 32bit accesses are supported`
482			`we_o <= #1 1'b0; // read only`
483
484			`if (vmem_ack \| cur_ack)`
485			`cti_o <= #1 cti; // cycle type`
486
487			`bte_o <= #1 2'b00; // linear burst`
488			`end`
489
490	34	rherveille	`//`
491	30	rherveille	`// video-data buffer (temporary store data read from video memory)`
492	19	rherveille	`vga_fifo #(4, 32) data_fifo (`
493			`.clk(clk_i),`
494	17	rherveille	`.aclr(1'b1),`
495	19	rherveille	`.sclr(sclr),`
496			`.d(dat_i),`
497	17	rherveille	`.wreq(vmem_ack),`
498	19	rherveille	`.q(data_fifo_q),`
499			`.rreq(data_fifo_rreq),`
500			`.empty(data_fifo_empty),`

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_wb_master.v] - Blame information for rev 45