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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant enhanced VGA/LCD Core            ////
////  Wishbone slave interface                                   ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/vga_lcd ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_wb_slave.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
//
//  $Date: 2002-02-07 05:42:10 $
//  $Revision: 1.6 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
 
 
`include "timescale.v"
`include "vga_defines.v"
 
module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,
                bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
                cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
                vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
                Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
 
        //
        // inputs & outputs
        //
 
        // wishbone slave interface
        input         CLK_I;
        input         RST_I;
        input         nRESET;
        input  [11:2] ADR_I;
        input  [31:0] DAT_I;
        output [31:0] DAT_O;
        reg [31:0] DAT_O;
        input  [ 3:0] SEL_I;
        input         WE_I;
        input         STB_I;
        input         CYC_I;
        output        ACK_O;
        reg ACK_O;
        output        ERR_O;
        reg ERR_O;
        output        INTA_O;
        reg INTA_O;
 
        // control register settings
        output bl;         // blanking level
        output csl;        // composite sync level
        output vsl;        // vsync level
        output hsl;        // hsync level
        output pc;         // pseudo color
        output [1:0] cd;   // color depth
        output [1:0] vbl;  // video memory burst length
        output cbsw;       // clut bank switch enable
        output vbsw;       // video memory bank switch enable
        output ven;        // video system enable
 
        // hardware cursor settings
        output         cursor0_en;
        output [31: 0] cursor0_xy;
        output [31:11] cursor0_ba;   // cursor0 base address
        output         cursor0_ld;   // reload cursor0 from video memory
        output         cursor1_en;
        output [31: 0] cursor1_xy;
        output [31:11] cursor1_ba;   // cursor1 base address
        output         cursor1_ld;   // reload cursor1 from video memory
 
        reg [31: 0] cursor0_xy;
        reg [31:11] cursor0_ba;
        reg         cursor0_ld;
        reg [31: 0] cursor1_xy;
        reg [31:11] cursor1_ba;
        reg         cursor1_ld;
 
        // status register inputs
        input avmp;          // active video memory page
        input acmp;          // active clut memory page
        input vbsint_in;     // bank switch interrupt request
        input cbsint_in;     // clut switch interrupt request
        input hint_in;       // hsync interrupt request
        input vint_in;       // vsync interrupt request
        input luint_in;      // line fifo underrun interrupt request
        input sint_in;       // system error interrupt request
 
        // Horizontal Timing Register
        output [ 7:0] Thsync;
        output [ 7:0] Thgdel;
        output [15:0] Thgate;
        output [15:0] Thlen;
 
        // Vertical Timing Register
        output [ 7:0] Tvsync;
        output [ 7:0] Tvgdel;
        output [15:0] Tvgate;
        output [15:0] Tvlen;
 
        // video base addresses
        output [31:2] VBARa;
        reg [31:2] VBARa;
        output [31:2] VBARb;
        reg [31:2] VBARb;
 
        // color lookup table signals
        output        clut_acc;
        input         clut_ack;
        input  [23:0] clut_q;
 
 
        //
        // variable declarations
        //
        parameter REG_ADR_HIBIT = 3;
 
        wire [REG_ADR_HIBIT:0] REG_ADR  = ADR_I[REG_ADR_HIBIT +2 : 2];
        wire                   CLUT_ADR = ADR_I[11];
 
        parameter [REG_ADR_HIBIT : 0] CTRL_ADR  = 4'b0000;
        parameter [REG_ADR_HIBIT : 0] STAT_ADR  = 4'b0001;
        parameter [REG_ADR_HIBIT : 0] HTIM_ADR  = 4'b0010;
        parameter [REG_ADR_HIBIT : 0] VTIM_ADR  = 4'b0011;
        parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 4'b0100;
        parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 4'b0101;
        parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 4'b0110;
        parameter [REG_ADR_HIBIT : 0] C0XY_ADR  = 4'b1000;
        parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 4'b1001;
        parameter [REG_ADR_HIBIT : 0] C1XY_ADR  = 4'b1010;
        parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 4'b1011;
 
 
        reg [31:0] ctrl, stat, htim, vtim, hvlen;
        wire hint, vint, vbsint, cbsint, luint, sint;
        wire hie, vie, vbsie, cbsie;
        wire acc, acc32, reg_acc, reg_wacc;
 
 
        reg [31:0] reg_dato; // data output from registers
 
        //
        // Module body
        //
 
        assign acc      =  CYC_I & STB_I;
        assign acc32    = (SEL_I == 4'b1111);
        assign clut_acc =  CLUT_ADR & acc & acc32;
        assign reg_acc  = !CLUT_ADR & acc & acc32;
        assign reg_wacc =  reg_acc & WE_I;
 
        always@(posedge CLK_I)
                ACK_O <= #1 ((reg_acc & acc32) | clut_ack) & !ACK_O;
 
        always@(posedge CLK_I)
                ERR_O <= #1 acc & !acc32;
 
 
        // generate registers
        always@(posedge CLK_I or negedge nRESET)
        begin : gen_regs
                if(!nRESET)
                        begin
                                htim  <= #1 0;
                                vtim  <= #1 0;
                                hvlen <= #1 0;
                                VBARa <= #1 0;
                                VBARb <= #1 0;
                        end
                else if (RST_I)
                        begin
                                htim  <= #1 0;
                                vtim  <= #1 0;
                                hvlen <= #1 0;
                                VBARa <= #1 0;
                                VBARb <= #1 0;
                        end
                else if (reg_wacc)
                        case (ADR_I)    // synopsis full_case parallel_case
                                HTIM_ADR  : htim       <= #1 DAT_I;
                                VTIM_ADR  : vtim       <= #1 DAT_I;
                                HVLEN_ADR : hvlen      <= #1 DAT_I;
                                VBARA_ADR : VBARa      <= #1 DAT_I[31: 2];
                                VBARB_ADR : VBARb      <= #1 DAT_I[31: 2];
                                C0XY_ADR  : cursor0_xy <= #1 DAT_I[31: 0];
                                C0BAR_ADR : cursor0_ba <= #1 DAT_I[31:11];
                                C1XY_ADR  : cursor1_xy <= #1 DAT_I[31: 0];
                                C1BAR_ADR : cursor1_ba <= #1 DAT_I[31:11];
                        endcase
        end
 
        always@(posedge CLK_I)
                begin
                        cursor0_ld <= #1 reg_wacc && (ADR_I == C0BAR_ADR);
                        cursor1_ld <= #1 reg_wacc && (ADR_I == C1BAR_ADR);
                end
 
        // generate control register
        always@(posedge CLK_I or negedge nRESET)
                if (!nRESET)
                        ctrl <= #1 0;
                else if (RST_I)
                        ctrl <= #1 0;
                else if (reg_wacc & (REG_ADR == CTRL_ADR) )
                        ctrl <= #1 DAT_I;
                else
                        begin
                                ctrl[6] <= #1 ctrl[6] & !cbsint_in;
                                ctrl[5] <= #1 ctrl[5] & !vbsint_in;
                        end
 
 
        // generate status register
        always@(posedge CLK_I or negedge nRESET)
                if (!nRESET)
                        stat <= #1 0;
                else if (RST_I)
                        stat <= #1 0;
                else
                        begin
                                `ifdef VGA_HWC1
                                        stat[21] <= #1 1'b1;
                                `else
                                        stat[21] <= #1 1'b0;
                                `endif
                                `ifdef VGA_HWC0
                                        stat[20] <= #1 1'b1;
                                `else
                                        stat[20] <= #1 1'b0;
                                `endif
 
                                stat[17] <= #1 acmp;
                                stat[16] <= #1 avmp;
 
                                if (reg_wacc & (REG_ADR == STAT_ADR) )
                                        begin
                                                stat[7] <= #1 cbsint_in | (stat[7] & !DAT_I[7]);
                                                stat[6] <= #1 vbsint_in | (stat[6] & !DAT_I[6]);
                                                stat[5] <= #1 hint_in   | (stat[5] & !DAT_I[5]);
                                                stat[4] <= #1 vint_in   | (stat[4] & !DAT_I[4]);
                                                stat[1] <= #1 luint_in  | (stat[3] & !DAT_I[1]);
                                                stat[0] <= #1 sint_in   | (stat[0] & !DAT_I[0]);
                                        end
                                else
                                        begin
                                                stat[7] <= #1 stat[7] | cbsint_in;
                                                stat[6] <= #1 stat[6] | vbsint_in;
                                                stat[5] <= #1 stat[5] | hint_in;
                                                stat[4] <= #1 stat[4] | vint_in;
                                                stat[1] <= #1 stat[1] | luint_in;
                                                stat[0] <= #1 stat[0] | sint_in;
                                        end
                        end
 
 
        // decode control register
        assign cursor1_en = ctrl[21];
        assign cursor0_en = ctrl[20];
        assign bl         = ctrl[15];
        assign csl        = ctrl[14];
        assign vsl        = ctrl[13];
        assign hsl        = ctrl[12];
        assign pc         = ctrl[11];
        assign cd         = ctrl[10:9];
        assign vbl        = ctrl[8:7];
        assign cbsw       = ctrl[6];
        assign vbsw       = ctrl[5];
        assign cbsie      = ctrl[4];
        assign vbsie      = ctrl[3];
        assign hie        = ctrl[2];
        assign vie        = ctrl[1];
        assign ven        = ctrl[0];
 
        // decode status register
        assign cbsint = stat[7];
        assign vbsint = stat[6];
        assign hint   = stat[5];
        assign vint   = stat[4];
        assign luint  = stat[1];
        assign sint   = stat[0];
 
        // decode Horizontal Timing Register
        assign Thsync = htim[31:24];
        assign Thgdel = htim[23:16];
        assign Thgate = htim[15:0];
        assign Thlen  = hvlen[31:16];
 
        // decode Vertical Timing Register
        assign Tvsync = vtim[31:24];
        assign Tvgdel = vtim[23:16];
        assign Tvgate = vtim[15:0];
        assign Tvlen  = hvlen[15:0];
 
 
        // assign output
        always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp)
        case (REG_ADR) // synopsis full_case parallel_case
                CTRL_ADR  : reg_dato = ctrl;
                STAT_ADR  : reg_dato = stat;
                HTIM_ADR  : reg_dato = htim;
                VTIM_ADR  : reg_dato = vtim;
                HVLEN_ADR : reg_dato = hvlen;
                VBARA_ADR : reg_dato = {VBARa, 2'b0};
                VBARB_ADR : reg_dato = {VBARb, 2'b0};
                C0XY_ADR  : reg_dato = cursor0_xy;
                C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};
                C1XY_ADR  : reg_dato = cursor1_xy;
                C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};
                default   : reg_dato = 32'h0000_0000;
        endcase
 
        always@(posedge CLK_I)
                DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
 
        // generate interrupt request signal
        always@(posedge CLK_I)
                INTA_O <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
endmodule
 
 

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	30	rherveille	`//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////`
4	23	rherveille	`//// Wishbone slave interface ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	30	rherveille	`//// Copyright (C) 2001, 2002 Richard Herveille ////`
15	23	rherveille	`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	17	rherveille	`//`
40	30	rherveille	`// $Id: vga_wb_slave.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $`
41	17	rherveille	`//`
42	30	rherveille	`// $Date: 2002-02-07 05:42:10 $`
43			`// $Revision: 1.6 $`
44	23	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	17	rherveille
51	23	rherveille
52	17	rherveille	`include "timescale.v"
53	30	rherveille	`include "vga_defines.v"
54	17	rherveille
55			`module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,`
56	30	rherveille	`bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,`
57			`cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,`
58			`vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,`
59	19	rherveille	`Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);`
60	17	rherveille
61			`//`
62			`// inputs & outputs`
63			`//`
64
65			`// wishbone slave interface`
66			`input CLK_I;`
67			`input RST_I;`
68			`input nRESET;`
69	19	rherveille	`input [11:2] ADR_I;`
70	17	rherveille	`input [31:0] DAT_I;`
71			`output [31:0] DAT_O;`
72			`reg [31:0] DAT_O;`
73			`input [ 3:0] SEL_I;`
74			`input WE_I;`
75			`input STB_I;`
76			`input CYC_I;`
77			`output ACK_O;`
78	19	rherveille	`reg ACK_O;`
79	17	rherveille	`output ERR_O;`
80	19	rherveille	`reg ERR_O;`
81	17	rherveille	`output INTA_O;`
82	19	rherveille	`reg INTA_O;`
83	17	rherveille
84			`// control register settings`
85	30	rherveille	`output bl; // blanking level`
86			`output csl; // composite sync level`
87			`output vsl; // vsync level`
88			`output hsl; // hsync level`
89			`output pc; // pseudo color`
90	17	rherveille	`output [1:0] cd; // color depth`
91			`output [1:0] vbl; // video memory burst length`
92	30	rherveille	`output cbsw; // clut bank switch enable`
93			`output vbsw; // video memory bank switch enable`
94			`output ven; // video system enable`
95	17	rherveille
96	30	rherveille	`// hardware cursor settings`
97			`output cursor0_en;`
98			`output [31: 0] cursor0_xy;`
99			`output [31:11] cursor0_ba; // cursor0 base address`
100			`output cursor0_ld; // reload cursor0 from video memory`
101			`output cursor1_en;`
102			`output [31: 0] cursor1_xy;`
103			`output [31:11] cursor1_ba; // cursor1 base address`
104			`output cursor1_ld; // reload cursor1 from video memory`
105
106			`reg [31: 0] cursor0_xy;`
107			`reg [31:11] cursor0_ba;`
108			`reg cursor0_ld;`
109			`reg [31: 0] cursor1_xy;`
110			`reg [31:11] cursor1_ba;`
111			`reg cursor1_ld;`
112
113	17	rherveille	`// status register inputs`
114	19	rherveille	`input avmp; // active video memory page`
115			`input acmp; // active clut memory page`
116			`input vbsint_in; // bank switch interrupt request`
117			`input cbsint_in; // clut switch interrupt request`
118			`input hint_in; // hsync interrupt request`
119			`input vint_in; // vsync interrupt request`
120			`input luint_in; // line fifo underrun interrupt request`
121			`input sint_in; // system error interrupt request`
122	17	rherveille
123			`// Horizontal Timing Register`
124			`output [ 7:0] Thsync;`
125			`output [ 7:0] Thgdel;`
126			`output [15:0] Thgate;`
127			`output [15:0] Thlen;`
128
129			`// Vertical Timing Register`
130			`output [ 7:0] Tvsync;`
131			`output [ 7:0] Tvgdel;`
132			`output [15:0] Tvgate;`
133			`output [15:0] Tvlen;`
134
135	19	rherveille	`// video base addresses`
136	30	rherveille	`output [31:2] VBARa;`
137			`reg [31:2] VBARa;`
138			`output [31:2] VBARb;`
139			`reg [31:2] VBARb;`
140	17	rherveille
141	19	rherveille	`// color lookup table signals`
142			`output clut_acc;`
143			`input clut_ack;`
144			`input [23:0] clut_q;`
145
146
147	17	rherveille	`//`
148			`// variable declarations`
149			`//`
150	30	rherveille	`parameter REG_ADR_HIBIT = 3;`
151	19	rherveille
152	30	rherveille	`wire [REG_ADR_HIBIT:0] REG_ADR = ADR_I[REG_ADR_HIBIT +2 : 2];`
153			`wire CLUT_ADR = ADR_I[11];`
154	17	rherveille
155	30	rherveille	`parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 4'b0000;`
156			`parameter [REG_ADR_HIBIT : 0] STAT_ADR = 4'b0001;`
157			`parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 4'b0010;`
158			`parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 4'b0011;`
159			`parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 4'b0100;`
160			`parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 4'b0101;`
161			`parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 4'b0110;`
162			`parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 4'b1000;`
163			`parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 4'b1001;`
164			`parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 4'b1010;`
165			`parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 4'b1011;`
166	17	rherveille
167	30	rherveille
168	17	rherveille	`reg [31:0] ctrl, stat, htim, vtim, hvlen;`
169	19	rherveille	`wire hint, vint, vbsint, cbsint, luint, sint;`
170			`wire hie, vie, vbsie, cbsie;`
171			`wire acc, acc32, reg_acc, reg_wacc;`
172	17	rherveille
173	19	rherveille
174			`reg [31:0] reg_dato; // data output from registers`
175
176	17	rherveille	`//`
177			`// Module body`
178			`//`
179
180	19	rherveille	`assign acc = CYC_I & STB_I;`
181			`assign acc32 = (SEL_I == 4'b1111);`
182			`assign clut_acc = CLUT_ADR & acc & acc32;`
183			`assign reg_acc = !CLUT_ADR & acc & acc32;`
184			`assign reg_wacc = reg_acc & WE_I;`
185	17	rherveille
186	19	rherveille	`always@(posedge CLK_I)`
187			`ACK_O <= #1 ((reg_acc & acc32) \| clut_ack) & !ACK_O;`
188	17	rherveille
189	19	rherveille	`always@(posedge CLK_I)`
190			`ERR_O <= #1 acc & !acc32;`
191
192
193	17	rherveille	`// generate registers`
194			`always@(posedge CLK_I or negedge nRESET)`
195			`begin : gen_regs`
196			`if(!nRESET)`
197			`begin`
198			`htim <= #1 0;`
199			`vtim <= #1 0;`
200			`hvlen <= #1 0;`
201			`VBARa <= #1 0;`
202			`VBARb <= #1 0;`
203			`end`
204			`else if (RST_I)`
205			`begin`
206			`htim <= #1 0;`
207			`vtim <= #1 0;`
208			`hvlen <= #1 0;`
209			`VBARa <= #1 0;`
210			`VBARb <= #1 0;`
211			`end`
212	19	rherveille	`else if (reg_wacc)`
213	17	rherveille	`case (ADR_I) // synopsis full_case parallel_case`
214	30	rherveille	`HTIM_ADR : htim <= #1 DAT_I;`
215			`VTIM_ADR : vtim <= #1 DAT_I;`
216			`HVLEN_ADR : hvlen <= #1 DAT_I;`
217			`VBARA_ADR : VBARa <= #1 DAT_I[31: 2];`
218			`VBARB_ADR : VBARb <= #1 DAT_I[31: 2];`
219			`C0XY_ADR : cursor0_xy <= #1 DAT_I[31: 0];`
220			`C0BAR_ADR : cursor0_ba <= #1 DAT_I[31:11];`
221			`C1XY_ADR : cursor1_xy <= #1 DAT_I[31: 0];`
222			`C1BAR_ADR : cursor1_ba <= #1 DAT_I[31:11];`
223	17	rherveille	`endcase`
224			`end`
225
226	30	rherveille	`always@(posedge CLK_I)`
227			`begin`
228			`cursor0_ld <= #1 reg_wacc && (ADR_I == C0BAR_ADR);`
229			`cursor1_ld <= #1 reg_wacc && (ADR_I == C1BAR_ADR);`
230			`end`
231	17	rherveille
232			`// generate control register`
233			`always@(posedge CLK_I or negedge nRESET)`
234			`if (!nRESET)`
235			`ctrl <= #1 0;`
236			`else if (RST_I)`
237			`ctrl <= #1 0;`
238	19	rherveille	`else if (reg_wacc & (REG_ADR == CTRL_ADR) )`
239	17	rherveille	`ctrl <= #1 DAT_I;`
240			`else`
241			`begin`
242	19	rherveille	`ctrl[6] <= #1 ctrl[6] & !cbsint_in;`
243			`ctrl[5] <= #1 ctrl[5] & !vbsint_in;`
244	17	rherveille	`end`
245
246
247			`// generate status register`
248			`always@(posedge CLK_I or negedge nRESET)`
249			`if (!nRESET)`
250			`stat <= #1 0;`
251			`else if (RST_I)`
252			`stat <= #1 0;`
253			`else`
254			`begin`
255	30	rherveille	`ifdef VGA_HWC1
256			`stat[21] <= #1 1'b1;`
257			`else
258			`stat[21] <= #1 1'b0;`
259			`endif
260			`ifdef VGA_HWC0
261			`stat[20] <= #1 1'b1;`
262			`else
263			`stat[20] <= #1 1'b0;`
264			`endif
265
266	17	rherveille	`stat[17] <= #1 acmp;`
267			`stat[16] <= #1 avmp;`
268	30	rherveille
269	19	rherveille	`if (reg_wacc & (REG_ADR == STAT_ADR) )`
270	17	rherveille	`begin`
271	19	rherveille	`stat[7] <= #1 cbsint_in \| (stat[7] & !DAT_I[7]);`
272			`stat[6] <= #1 vbsint_in \| (stat[6] & !DAT_I[6]);`
273			`stat[5] <= #1 hint_in \| (stat[5] & !DAT_I[5]);`
274			`stat[4] <= #1 vint_in \| (stat[4] & !DAT_I[4]);`
275			`stat[1] <= #1 luint_in \| (stat[3] & !DAT_I[1]);`
276			`stat[0] <= #1 sint_in \| (stat[0] & !DAT_I[0]);`
277	17	rherveille	`end`
278			`else`
279			`begin`
280	19	rherveille	`stat[7] <= #1 stat[7] \| cbsint_in;`
281			`stat[6] <= #1 stat[6] \| vbsint_in;`
282	17	rherveille	`stat[5] <= #1 stat[5] \| hint_in;`
283			`stat[4] <= #1 stat[4] \| vint_in;`
284			`stat[1] <= #1 stat[1] \| luint_in;`
285			`stat[0] <= #1 stat[0] \| sint_in;`
286			`end`
287			`end`
288
289
290			`// decode control register`
291	30	rherveille	`assign cursor1_en = ctrl[21];`
292			`assign cursor0_en = ctrl[20];`
293			`assign bl = ctrl[15];`
294			`assign csl = ctrl[14];`
295			`assign vsl = ctrl[13];`
296			`assign hsl = ctrl[12];`
297			`assign pc = ctrl[11];`
298			`assign cd = ctrl[10:9];`
299			`assign vbl = ctrl[8:7];`
300			`assign cbsw = ctrl[6];`
301			`assign vbsw = ctrl[5];`
302			`assign cbsie = ctrl[4];`
303			`assign vbsie = ctrl[3];`
304			`assign hie = ctrl[2];`
305			`assign vie = ctrl[1];`
306			`assign ven = ctrl[0];`
307	17	rherveille
308			`// decode status register`
309	19	rherveille	`assign cbsint = stat[7];`
310			`assign vbsint = stat[6];`
311			`assign hint = stat[5];`
312			`assign vint = stat[4];`
313			`assign luint = stat[1];`
314			`assign sint = stat[0];`
315	17	rherveille
316			`// decode Horizontal Timing Register`
317			`assign Thsync = htim[31:24];`
318			`assign Thgdel = htim[23:16];`
319			`assign Thgate = htim[15:0];`
320			`assign Thlen = hvlen[31:16];`
321
322			`// decode Vertical Timing Register`
323			`assign Tvsync = vtim[31:24];`
324			`assign Tvgdel = vtim[23:16];`
325			`assign Tvgate = vtim[15:0];`
326			`assign Tvlen = hvlen[15:0];`
327
328
329			`// assign output`
330	19	rherveille	`always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp)`
331			`case (REG_ADR) // synopsis full_case parallel_case`
332			`CTRL_ADR : reg_dato = ctrl;`
333			`STAT_ADR : reg_dato = stat;`
334			`HTIM_ADR : reg_dato = htim;`
335			`VTIM_ADR : reg_dato = vtim;`
336			`HVLEN_ADR : reg_dato = hvlen;`
337			`VBARA_ADR : reg_dato = {VBARa, 2'b0};`
338			`VBARB_ADR : reg_dato = {VBARb, 2'b0};`
339	30	rherveille	`C0XY_ADR : reg_dato = cursor0_xy;`
340			`C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};`
341			`C1XY_ADR : reg_dato = cursor1_xy;`
342			`C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};`
343	19	rherveille	`default : reg_dato = 32'h0000_0000;`
344	17	rherveille	`endcase`
345
346	19	rherveille	`always@(posedge CLK_I)`
347			`DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};`
348
349	17	rherveille	`// generate interrupt request signal`
350	19	rherveille	`always@(posedge CLK_I)`
351			`INTA_O <= #1 (hint & hie) \| (vint & vie) \| (vbsint & vbsie) \| (cbsint & cbsie) \| luint \| sint;`
352	17	rherveille	`endmodule`
353	19	rherveille
354	30	rherveille

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