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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant enhanced VGA/LCD Core            ////
////  Wishbone slave interface                                   ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/vga_lcd ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: vga_wb_slave.v,v 1.7 2002-02-25 06:13:44 rherveille Exp $
//
//  $Date: 2002-02-25 06:13:44 $
//  $Revision: 1.7 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.6  2002/02/07 05:42:10  rherveille
//               Fixed some bugs discovered by modified testbench
//               Removed / Changed some strange logic constructions
//               Started work on hardware cursor support (not finished yet)
//               Changed top-level name to vga_enh_top.v
//
 
 
`include "timescale.v"
`include "vga_defines.v"
 
module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,
                bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
                cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
                vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
                Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
 
        //
        // inputs & outputs
        //
 
        // wishbone slave interface
        input         CLK_I;
        input         RST_I;
        input         nRESET;
        input  [11:2] ADR_I;
        input  [31:0] DAT_I;
        output [31:0] DAT_O;
        reg [31:0] DAT_O;
        input  [ 3:0] SEL_I;
        input         WE_I;
        input         STB_I;
        input         CYC_I;
        output        ACK_O;
        reg ACK_O;
        output        ERR_O;
        reg ERR_O;
        output        INTA_O;
        reg INTA_O;
 
        // control register settings
        output bl;         // blanking level
        output csl;        // composite sync level
        output vsl;        // vsync level
        output hsl;        // hsync level
        output pc;         // pseudo color
        output [1:0] cd;   // color depth
        output [1:0] vbl;  // video memory burst length
        output cbsw;       // clut bank switch enable
        output vbsw;       // video memory bank switch enable
        output ven;        // video system enable
 
        // hardware cursor settings
        output         cursor0_en;
        output [31: 0] cursor0_xy;
        output [31:11] cursor0_ba;   // cursor0 base address
        output         cursor0_ld;   // reload cursor0 from video memory
        output         cursor1_en;
        output [31: 0] cursor1_xy;
        output [31:11] cursor1_ba;   // cursor1 base address
        output         cursor1_ld;   // reload cursor1 from video memory
 
        reg [31: 0] cursor0_xy;
        reg [31:11] cursor0_ba;
        reg         cursor0_ld;
        reg [31: 0] cursor1_xy;
        reg [31:11] cursor1_ba;
        reg         cursor1_ld;
 
        // status register inputs
        input avmp;          // active video memory page
        input acmp;          // active clut memory page
        input vbsint_in;     // bank switch interrupt request
        input cbsint_in;     // clut switch interrupt request
        input hint_in;       // hsync interrupt request
        input vint_in;       // vsync interrupt request
        input luint_in;      // line fifo underrun interrupt request
        input sint_in;       // system error interrupt request
 
        // Horizontal Timing Register
        output [ 7:0] Thsync;
        output [ 7:0] Thgdel;
        output [15:0] Thgate;
        output [15:0] Thlen;
 
        // Vertical Timing Register
        output [ 7:0] Tvsync;
        output [ 7:0] Tvgdel;
        output [15:0] Tvgate;
        output [15:0] Tvlen;
 
        // video base addresses
        output [31:2] VBARa;
        reg [31:2] VBARa;
        output [31:2] VBARb;
        reg [31:2] VBARb;
 
        // color lookup table signals
        output        clut_acc;
        input         clut_ack;
        input  [23:0] clut_q;
 
 
        //
        // variable declarations
        //
        parameter REG_ADR_HIBIT = 3;
 
        wire [REG_ADR_HIBIT:0] REG_ADR  = ADR_I[REG_ADR_HIBIT +2 : 2];
        wire                   CLUT_ADR = ADR_I[11];
 
        parameter [REG_ADR_HIBIT : 0] CTRL_ADR  = 4'b0000;
        parameter [REG_ADR_HIBIT : 0] STAT_ADR  = 4'b0001;
        parameter [REG_ADR_HIBIT : 0] HTIM_ADR  = 4'b0010;
        parameter [REG_ADR_HIBIT : 0] VTIM_ADR  = 4'b0011;
        parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 4'b0100;
        parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 4'b0101;
        parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 4'b0110;
        parameter [REG_ADR_HIBIT : 0] C0XY_ADR  = 4'b1000;
        parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 4'b1001;
        parameter [REG_ADR_HIBIT : 0] C1XY_ADR  = 4'b1010;
        parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 4'b1011;
 
 
        reg [31:0] ctrl, stat, htim, vtim, hvlen;
        wire hint, vint, vbsint, cbsint, luint, sint;
        wire hie, vie, vbsie, cbsie;
        wire acc, acc32, reg_acc, reg_wacc;
 
 
        reg [31:0] reg_dato; // data output from registers
 
        //
        // Module body
        //
 
        assign acc      =  CYC_I & STB_I;
        assign acc32    = (SEL_I == 4'b1111);
        assign clut_acc =  CLUT_ADR & acc & acc32;
        assign reg_acc  = !CLUT_ADR & acc & acc32;
        assign reg_wacc =  reg_acc & WE_I;
 
        always@(posedge CLK_I)
                ACK_O <= #1 ((reg_acc & acc32) | clut_ack) & !ACK_O;
 
        always@(posedge CLK_I)
                ERR_O <= #1 acc & !acc32;
 
 
        // generate registers
        always@(posedge CLK_I or negedge nRESET)
        begin : gen_regs
                if(!nRESET)
                        begin
                                htim       <= #1 0;
                                vtim       <= #1 0;
                                hvlen      <= #1 0;
                                VBARa      <= #1 0;
                                VBARb      <= #1 0;
                                cursor0_xy <= #1 0;
                                cursor0_ba <= #1 0;
                                cursor1_xy <= #1 0;
                                cursor1_ba <= #1 0;
                        end
                else if (RST_I)
                        begin
                                htim       <= #1 0;
                                vtim       <= #1 0;
                                hvlen      <= #1 0;
                                VBARa      <= #1 0;
                                VBARb      <= #1 0;
                                cursor0_xy <= #1 0;
                                cursor0_ba <= #1 0;
                                cursor1_xy <= #1 0;
                                cursor1_ba <= #1 0;
                        end
                else if (reg_wacc)
                        case (ADR_I)    // synopsis full_case parallel_case
                                HTIM_ADR  : htim       <= #1 DAT_I;
                                VTIM_ADR  : vtim       <= #1 DAT_I;
                                HVLEN_ADR : hvlen      <= #1 DAT_I;
                                VBARA_ADR : VBARa      <= #1 DAT_I[31: 2];
                                VBARB_ADR : VBARb      <= #1 DAT_I[31: 2];
                                C0XY_ADR  : cursor0_xy <= #1 DAT_I[31: 0];
                                C0BAR_ADR : cursor0_ba <= #1 DAT_I[31:11];
                                C1XY_ADR  : cursor1_xy <= #1 DAT_I[31: 0];
                                C1BAR_ADR : cursor1_ba <= #1 DAT_I[31:11];
                        endcase
        end
 
        always@(posedge CLK_I)
                begin
                        cursor0_ld <= #1 reg_wacc && (ADR_I == C0BAR_ADR);
                        cursor1_ld <= #1 reg_wacc && (ADR_I == C1BAR_ADR);
                end
 
        // generate control register
        always@(posedge CLK_I or negedge nRESET)
                if (!nRESET)
                        ctrl <= #1 0;
                else if (RST_I)
                        ctrl <= #1 0;
                else if (reg_wacc & (REG_ADR == CTRL_ADR) )
                        ctrl <= #1 DAT_I;
                else
                        begin
                                ctrl[6] <= #1 ctrl[6] & !cbsint_in;
                                ctrl[5] <= #1 ctrl[5] & !vbsint_in;
                        end
 
 
        // generate status register
        always@(posedge CLK_I or negedge nRESET)
                if (!nRESET)
                        stat <= #1 0;
                else if (RST_I)
                        stat <= #1 0;
                else
                        begin
                                `ifdef VGA_HWC1
                                        stat[21] <= #1 1'b1;
                                `else
                                        stat[21] <= #1 1'b0;
                                `endif
                                `ifdef VGA_HWC0
                                        stat[20] <= #1 1'b1;
                                `else
                                        stat[20] <= #1 1'b0;
                                `endif
 
                                stat[17] <= #1 acmp;
                                stat[16] <= #1 avmp;
 
                                if (reg_wacc & (REG_ADR == STAT_ADR) )
                                        begin
                                                stat[7] <= #1 cbsint_in | (stat[7] & !DAT_I[7]);
                                                stat[6] <= #1 vbsint_in | (stat[6] & !DAT_I[6]);
                                                stat[5] <= #1 hint_in   | (stat[5] & !DAT_I[5]);
                                                stat[4] <= #1 vint_in   | (stat[4] & !DAT_I[4]);
                                                stat[1] <= #1 luint_in  | (stat[3] & !DAT_I[1]);
                                                stat[0] <= #1 sint_in   | (stat[0] & !DAT_I[0]);
                                        end
                                else
                                        begin
                                                stat[7] <= #1 stat[7] | cbsint_in;
                                                stat[6] <= #1 stat[6] | vbsint_in;
                                                stat[5] <= #1 stat[5] | hint_in;
                                                stat[4] <= #1 stat[4] | vint_in;
                                                stat[1] <= #1 stat[1] | luint_in;
                                                stat[0] <= #1 stat[0] | sint_in;
                                        end
                        end
 
 
        // decode control register
        assign cursor1_en = ctrl[21];
        assign cursor0_en = ctrl[20];
        assign bl         = ctrl[15];
        assign csl        = ctrl[14];
        assign vsl        = ctrl[13];
        assign hsl        = ctrl[12];
        assign pc         = ctrl[11];
        assign cd         = ctrl[10:9];
        assign vbl        = ctrl[8:7];
        assign cbsw       = ctrl[6];
        assign vbsw       = ctrl[5];
        assign cbsie      = ctrl[4];
        assign vbsie      = ctrl[3];
        assign hie        = ctrl[2];
        assign vie        = ctrl[1];
        assign ven        = ctrl[0];
 
        // decode status register
        assign cbsint = stat[7];
        assign vbsint = stat[6];
        assign hint   = stat[5];
        assign vint   = stat[4];
        assign luint  = stat[1];
        assign sint   = stat[0];
 
        // decode Horizontal Timing Register
        assign Thsync = htim[31:24];
        assign Thgdel = htim[23:16];
        assign Thgate = htim[15:0];
        assign Thlen  = hvlen[31:16];
 
        // decode Vertical Timing Register
        assign Tvsync = vtim[31:24];
        assign Tvgdel = vtim[23:16];
        assign Tvgate = vtim[15:0];
        assign Tvlen  = hvlen[15:0];
 
 
        // assign output
        always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or
                cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba)
        case (REG_ADR) // synopsis full_case parallel_case
                CTRL_ADR  : reg_dato = ctrl;
                STAT_ADR  : reg_dato = stat;
                HTIM_ADR  : reg_dato = htim;
                VTIM_ADR  : reg_dato = vtim;
                HVLEN_ADR : reg_dato = hvlen;
                VBARA_ADR : reg_dato = {VBARa, 2'b0};
                VBARB_ADR : reg_dato = {VBARb, 2'b0};
                C0XY_ADR  : reg_dato = cursor0_xy;
                C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};
                C1XY_ADR  : reg_dato = cursor1_xy;
                C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};
                default   : reg_dato = 32'h0000_0000;
        endcase
 
        always@(posedge CLK_I)
                DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
 
        // generate interrupt request signal
        always@(posedge CLK_I)
                INTA_O <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
endmodule
 
 

Line No.	Rev	Author	Line
1	23	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	30	rherveille	`//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////`
4	23	rherveille	`//// Wishbone slave interface ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	30	rherveille	`//// Copyright (C) 2001, 2002 Richard Herveille ////`
15	23	rherveille	`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	17	rherveille	`//`
40	32	rherveille	`// $Id: vga_wb_slave.v,v 1.7 2002-02-25 06:13:44 rherveille Exp $`
41	17	rherveille	`//`
42	32	rherveille	`// $Date: 2002-02-25 06:13:44 $`
43			`// $Revision: 1.7 $`
44	23	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	32	rherveille	`// Revision 1.6 2002/02/07 05:42:10 rherveille`
51			`// Fixed some bugs discovered by modified testbench`
52			`// Removed / Changed some strange logic constructions`
53			`// Started work on hardware cursor support (not finished yet)`
54			`// Changed top-level name to vga_enh_top.v`
55			`//`
56	17	rherveille
57	23	rherveille
58	17	rherveille	`include "timescale.v"
59	30	rherveille	`include "vga_defines.v"
60	17	rherveille
61			`module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,`
62	30	rherveille	`bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,`
63			`cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,`
64			`vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,`
65	19	rherveille	`Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);`
66	17	rherveille
67			`//`
68			`// inputs & outputs`
69			`//`
70
71			`// wishbone slave interface`
72			`input CLK_I;`
73			`input RST_I;`
74			`input nRESET;`
75	19	rherveille	`input [11:2] ADR_I;`
76	17	rherveille	`input [31:0] DAT_I;`
77			`output [31:0] DAT_O;`
78			`reg [31:0] DAT_O;`
79			`input [ 3:0] SEL_I;`
80			`input WE_I;`
81			`input STB_I;`
82			`input CYC_I;`
83			`output ACK_O;`
84	19	rherveille	`reg ACK_O;`
85	17	rherveille	`output ERR_O;`
86	19	rherveille	`reg ERR_O;`
87	17	rherveille	`output INTA_O;`
88	19	rherveille	`reg INTA_O;`
89	17	rherveille
90			`// control register settings`
91	30	rherveille	`output bl; // blanking level`
92			`output csl; // composite sync level`
93			`output vsl; // vsync level`
94			`output hsl; // hsync level`
95			`output pc; // pseudo color`
96	17	rherveille	`output [1:0] cd; // color depth`
97			`output [1:0] vbl; // video memory burst length`
98	30	rherveille	`output cbsw; // clut bank switch enable`
99			`output vbsw; // video memory bank switch enable`
100			`output ven; // video system enable`
101	17	rherveille
102	30	rherveille	`// hardware cursor settings`
103			`output cursor0_en;`
104			`output [31: 0] cursor0_xy;`
105			`output [31:11] cursor0_ba; // cursor0 base address`
106			`output cursor0_ld; // reload cursor0 from video memory`
107			`output cursor1_en;`
108			`output [31: 0] cursor1_xy;`
109			`output [31:11] cursor1_ba; // cursor1 base address`
110			`output cursor1_ld; // reload cursor1 from video memory`
111
112			`reg [31: 0] cursor0_xy;`
113			`reg [31:11] cursor0_ba;`
114			`reg cursor0_ld;`
115			`reg [31: 0] cursor1_xy;`
116			`reg [31:11] cursor1_ba;`
117			`reg cursor1_ld;`
118
119	17	rherveille	`// status register inputs`
120	19	rherveille	`input avmp; // active video memory page`
121			`input acmp; // active clut memory page`
122			`input vbsint_in; // bank switch interrupt request`
123			`input cbsint_in; // clut switch interrupt request`
124			`input hint_in; // hsync interrupt request`
125			`input vint_in; // vsync interrupt request`
126			`input luint_in; // line fifo underrun interrupt request`
127			`input sint_in; // system error interrupt request`
128	17	rherveille
129			`// Horizontal Timing Register`
130			`output [ 7:0] Thsync;`
131			`output [ 7:0] Thgdel;`
132			`output [15:0] Thgate;`
133			`output [15:0] Thlen;`
134
135			`// Vertical Timing Register`
136			`output [ 7:0] Tvsync;`
137			`output [ 7:0] Tvgdel;`
138			`output [15:0] Tvgate;`
139			`output [15:0] Tvlen;`
140
141	19	rherveille	`// video base addresses`
142	30	rherveille	`output [31:2] VBARa;`
143			`reg [31:2] VBARa;`
144			`output [31:2] VBARb;`
145			`reg [31:2] VBARb;`
146	17	rherveille
147	19	rherveille	`// color lookup table signals`
148			`output clut_acc;`
149			`input clut_ack;`
150			`input [23:0] clut_q;`
151
152
153	17	rherveille	`//`
154			`// variable declarations`
155			`//`
156	30	rherveille	`parameter REG_ADR_HIBIT = 3;`
157	19	rherveille
158	30	rherveille	`wire [REG_ADR_HIBIT:0] REG_ADR = ADR_I[REG_ADR_HIBIT +2 : 2];`
159			`wire CLUT_ADR = ADR_I[11];`
160	17	rherveille
161	30	rherveille	`parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 4'b0000;`
162			`parameter [REG_ADR_HIBIT : 0] STAT_ADR = 4'b0001;`
163			`parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 4'b0010;`
164			`parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 4'b0011;`
165			`parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 4'b0100;`
166			`parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 4'b0101;`
167			`parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 4'b0110;`
168			`parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 4'b1000;`
169			`parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 4'b1001;`
170			`parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 4'b1010;`
171			`parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 4'b1011;`
172	17	rherveille
173	30	rherveille
174	17	rherveille	`reg [31:0] ctrl, stat, htim, vtim, hvlen;`
175	19	rherveille	`wire hint, vint, vbsint, cbsint, luint, sint;`
176			`wire hie, vie, vbsie, cbsie;`
177			`wire acc, acc32, reg_acc, reg_wacc;`
178	17	rherveille
179	19	rherveille
180			`reg [31:0] reg_dato; // data output from registers`
181
182	17	rherveille	`//`
183			`// Module body`
184			`//`
185
186	19	rherveille	`assign acc = CYC_I & STB_I;`
187			`assign acc32 = (SEL_I == 4'b1111);`
188			`assign clut_acc = CLUT_ADR & acc & acc32;`
189			`assign reg_acc = !CLUT_ADR & acc & acc32;`
190			`assign reg_wacc = reg_acc & WE_I;`
191	17	rherveille
192	19	rherveille	`always@(posedge CLK_I)`
193			`ACK_O <= #1 ((reg_acc & acc32) \| clut_ack) & !ACK_O;`
194	17	rherveille
195	19	rherveille	`always@(posedge CLK_I)`
196			`ERR_O <= #1 acc & !acc32;`
197
198
199	17	rherveille	`// generate registers`
200			`always@(posedge CLK_I or negedge nRESET)`
201			`begin : gen_regs`
202			`if(!nRESET)`
203			`begin`
204	32	rherveille	`htim <= #1 0;`
205			`vtim <= #1 0;`
206			`hvlen <= #1 0;`
207			`VBARa <= #1 0;`
208			`VBARb <= #1 0;`
209			`cursor0_xy <= #1 0;`
210			`cursor0_ba <= #1 0;`
211			`cursor1_xy <= #1 0;`
212			`cursor1_ba <= #1 0;`
213	17	rherveille	`end`
214			`else if (RST_I)`
215			`begin`
216	32	rherveille	`htim <= #1 0;`
217			`vtim <= #1 0;`
218			`hvlen <= #1 0;`
219			`VBARa <= #1 0;`
220			`VBARb <= #1 0;`
221			`cursor0_xy <= #1 0;`
222			`cursor0_ba <= #1 0;`
223			`cursor1_xy <= #1 0;`
224			`cursor1_ba <= #1 0;`
225	17	rherveille	`end`
226	19	rherveille	`else if (reg_wacc)`
227	17	rherveille	`case (ADR_I) // synopsis full_case parallel_case`
228	30	rherveille	`HTIM_ADR : htim <= #1 DAT_I;`
229			`VTIM_ADR : vtim <= #1 DAT_I;`
230			`HVLEN_ADR : hvlen <= #1 DAT_I;`
231			`VBARA_ADR : VBARa <= #1 DAT_I[31: 2];`
232			`VBARB_ADR : VBARb <= #1 DAT_I[31: 2];`
233			`C0XY_ADR : cursor0_xy <= #1 DAT_I[31: 0];`
234			`C0BAR_ADR : cursor0_ba <= #1 DAT_I[31:11];`
235			`C1XY_ADR : cursor1_xy <= #1 DAT_I[31: 0];`
236			`C1BAR_ADR : cursor1_ba <= #1 DAT_I[31:11];`
237	17	rherveille	`endcase`
238			`end`
239
240	30	rherveille	`always@(posedge CLK_I)`
241			`begin`
242			`cursor0_ld <= #1 reg_wacc && (ADR_I == C0BAR_ADR);`
243			`cursor1_ld <= #1 reg_wacc && (ADR_I == C1BAR_ADR);`
244			`end`
245	17	rherveille
246			`// generate control register`
247			`always@(posedge CLK_I or negedge nRESET)`
248			`if (!nRESET)`
249			`ctrl <= #1 0;`
250			`else if (RST_I)`
251			`ctrl <= #1 0;`
252	19	rherveille	`else if (reg_wacc & (REG_ADR == CTRL_ADR) )`
253	17	rherveille	`ctrl <= #1 DAT_I;`
254			`else`
255			`begin`
256	19	rherveille	`ctrl[6] <= #1 ctrl[6] & !cbsint_in;`
257			`ctrl[5] <= #1 ctrl[5] & !vbsint_in;`
258	17	rherveille	`end`
259
260
261			`// generate status register`
262			`always@(posedge CLK_I or negedge nRESET)`
263			`if (!nRESET)`
264			`stat <= #1 0;`
265			`else if (RST_I)`
266			`stat <= #1 0;`
267			`else`
268			`begin`
269	30	rherveille	`ifdef VGA_HWC1
270			`stat[21] <= #1 1'b1;`
271			`else
272			`stat[21] <= #1 1'b0;`
273			`endif
274			`ifdef VGA_HWC0
275			`stat[20] <= #1 1'b1;`
276			`else
277			`stat[20] <= #1 1'b0;`
278			`endif
279
280	17	rherveille	`stat[17] <= #1 acmp;`
281			`stat[16] <= #1 avmp;`
282	30	rherveille
283	19	rherveille	`if (reg_wacc & (REG_ADR == STAT_ADR) )`
284	17	rherveille	`begin`
285	19	rherveille	`stat[7] <= #1 cbsint_in \| (stat[7] & !DAT_I[7]);`
286			`stat[6] <= #1 vbsint_in \| (stat[6] & !DAT_I[6]);`
287			`stat[5] <= #1 hint_in \| (stat[5] & !DAT_I[5]);`
288			`stat[4] <= #1 vint_in \| (stat[4] & !DAT_I[4]);`
289			`stat[1] <= #1 luint_in \| (stat[3] & !DAT_I[1]);`
290			`stat[0] <= #1 sint_in \| (stat[0] & !DAT_I[0]);`
291	17	rherveille	`end`
292			`else`
293			`begin`
294	19	rherveille	`stat[7] <= #1 stat[7] \| cbsint_in;`
295			`stat[6] <= #1 stat[6] \| vbsint_in;`
296	17	rherveille	`stat[5] <= #1 stat[5] \| hint_in;`
297			`stat[4] <= #1 stat[4] \| vint_in;`
298			`stat[1] <= #1 stat[1] \| luint_in;`
299			`stat[0] <= #1 stat[0] \| sint_in;`
300			`end`
301			`end`
302
303
304			`// decode control register`
305	30	rherveille	`assign cursor1_en = ctrl[21];`
306			`assign cursor0_en = ctrl[20];`
307			`assign bl = ctrl[15];`
308			`assign csl = ctrl[14];`
309			`assign vsl = ctrl[13];`
310			`assign hsl = ctrl[12];`
311			`assign pc = ctrl[11];`
312			`assign cd = ctrl[10:9];`
313			`assign vbl = ctrl[8:7];`
314			`assign cbsw = ctrl[6];`
315			`assign vbsw = ctrl[5];`
316			`assign cbsie = ctrl[4];`
317			`assign vbsie = ctrl[3];`
318			`assign hie = ctrl[2];`
319			`assign vie = ctrl[1];`
320			`assign ven = ctrl[0];`
321	17	rherveille
322			`// decode status register`
323	19	rherveille	`assign cbsint = stat[7];`
324			`assign vbsint = stat[6];`
325			`assign hint = stat[5];`
326			`assign vint = stat[4];`
327			`assign luint = stat[1];`
328			`assign sint = stat[0];`
329	17	rherveille
330			`// decode Horizontal Timing Register`
331			`assign Thsync = htim[31:24];`
332			`assign Thgdel = htim[23:16];`
333			`assign Thgate = htim[15:0];`
334			`assign Thlen = hvlen[31:16];`
335
336			`// decode Vertical Timing Register`
337			`assign Tvsync = vtim[31:24];`
338			`assign Tvgdel = vtim[23:16];`
339			`assign Tvgate = vtim[15:0];`
340			`assign Tvlen = hvlen[15:0];`
341
342
343			`// assign output`
344	32	rherveille	`always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or`
345			`cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba)`
346	19	rherveille	`case (REG_ADR) // synopsis full_case parallel_case`
347			`CTRL_ADR : reg_dato = ctrl;`
348			`STAT_ADR : reg_dato = stat;`
349			`HTIM_ADR : reg_dato = htim;`
350			`VTIM_ADR : reg_dato = vtim;`
351			`HVLEN_ADR : reg_dato = hvlen;`
352			`VBARA_ADR : reg_dato = {VBARa, 2'b0};`
353			`VBARB_ADR : reg_dato = {VBARb, 2'b0};`
354	30	rherveille	`C0XY_ADR : reg_dato = cursor0_xy;`
355			`C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};`
356			`C1XY_ADR : reg_dato = cursor1_xy;`
357			`C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};`
358	19	rherveille	`default : reg_dato = 32'h0000_0000;`
359	17	rherveille	`endcase`
360
361	19	rherveille	`always@(posedge CLK_I)`
362			`DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};`
363
364	17	rherveille	`// generate interrupt request signal`
365	19	rherveille	`always@(posedge CLK_I)`
366			`INTA_O <= #1 (hint & hie) \| (vint & vie) \| (vbsint & vbsie) \| (cbsint & cbsie) \| luint \| sint;`
367	17	rherveille	`endmodule`
368	19	rherveille
369	30	rherveille

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