1 |
16 |
rudi |
--
|
2 |
|
|
-- File pgen.vhd, Video Pixel Generator
|
3 |
|
|
-- Project: VGA
|
4 |
|
|
-- Author : Richard Herveille
|
5 |
|
|
-- rev.: 0.1 April 19th, 2001. Initial release
|
6 |
|
|
-- rev.: 1.0 July 15th, 2001. Removed synchronized registers; static settings don't require synchronization.
|
7 |
|
|
--
|
8 |
|
|
--
|
9 |
|
|
|
10 |
|
|
library ieee;
|
11 |
|
|
use ieee.std_logic_1164.all;
|
12 |
|
|
use ieee.std_logic_arith.all;
|
13 |
|
|
|
14 |
|
|
entity Pgen is
|
15 |
|
|
port(
|
16 |
|
|
mclk : in std_logic; -- master clock
|
17 |
|
|
pclk : in std_logic; -- pixel clock
|
18 |
|
|
|
19 |
|
|
ctrl_Ven : in std_logic; -- VideoEnable signal
|
20 |
|
|
|
21 |
|
|
-- horizontal timing settings
|
22 |
|
|
ctrl_HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg)
|
23 |
|
|
Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels)
|
24 |
|
|
Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels)
|
25 |
|
|
Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line)
|
26 |
|
|
Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line)
|
27 |
|
|
|
28 |
|
|
-- vertical timing settings
|
29 |
|
|
ctrl_VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg)
|
30 |
|
|
Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines)
|
31 |
|
|
Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines)
|
32 |
|
|
Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame)
|
33 |
|
|
Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame)
|
34 |
|
|
|
35 |
|
|
ctrl_CSyncL : in std_logic; -- composite sync pulse polarization level
|
36 |
|
|
ctrl_BlankL : in std_logic; -- blank signal polarization level
|
37 |
|
|
|
38 |
|
|
-- status outputs
|
39 |
|
|
eoh, -- end of horizontal
|
40 |
|
|
eov, -- end of vertical
|
41 |
|
|
Gate : out std_logic; -- vertical AND horizontal gate (logical AND function)
|
42 |
|
|
|
43 |
|
|
-- pixel control outputs
|
44 |
|
|
Hsync, -- horizontal sync pulse
|
45 |
|
|
Vsync, -- vertical sync pulse
|
46 |
|
|
Csync, -- composite sync: Hsync OR Vsync (logical OR function)
|
47 |
|
|
Blank : out std_logic -- blank signals
|
48 |
|
|
);
|
49 |
|
|
end entity Pgen;
|
50 |
|
|
|
51 |
|
|
architecture dataflow of Pgen is
|
52 |
|
|
--
|
53 |
|
|
-- Component declarations
|
54 |
|
|
--
|
55 |
|
|
component tgen is
|
56 |
|
|
port(
|
57 |
|
|
clk : in std_logic;
|
58 |
|
|
rst : in std_logic;
|
59 |
|
|
|
60 |
|
|
-- horizontal timing settings
|
61 |
|
|
HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg)
|
62 |
|
|
Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels)
|
63 |
|
|
Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels)
|
64 |
|
|
Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line)
|
65 |
|
|
Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line)
|
66 |
|
|
|
67 |
|
|
-- vertical timing settings
|
68 |
|
|
VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg)
|
69 |
|
|
Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines)
|
70 |
|
|
Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines)
|
71 |
|
|
Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame)
|
72 |
|
|
Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame)
|
73 |
|
|
|
74 |
|
|
CSyncL : in std_logic; -- composite sync pulse polarization level (pos/neg)
|
75 |
|
|
BlankL : in std_logic; -- blank signal polarization level
|
76 |
|
|
|
77 |
|
|
eol, -- end of line
|
78 |
|
|
eof, -- end of frame
|
79 |
|
|
gate, -- vertical AND horizontal gate (logical and function)
|
80 |
|
|
|
81 |
|
|
Hsync, -- horizontal sync pulse
|
82 |
|
|
Vsync, -- vertical sync pulse
|
83 |
|
|
Csync, -- composite sync pulse
|
84 |
|
|
Blank : out std_logic -- blank signal
|
85 |
|
|
);
|
86 |
|
|
end component tgen;
|
87 |
|
|
|
88 |
|
|
--
|
89 |
|
|
-- signals
|
90 |
|
|
--
|
91 |
|
|
signal eol, eof : std_logic;
|
92 |
|
|
begin
|
93 |
|
|
--
|
94 |
|
|
-- timing block
|
95 |
|
|
--
|
96 |
|
|
tblk: block
|
97 |
|
|
signal nVen : std_logic; -- video enable signal (active low)
|
98 |
|
|
begin
|
99 |
|
|
-- synchronize timing/control settings (from master-clock-domain to pixel-clock-domain)
|
100 |
|
|
sync_settings: process(pclk)
|
101 |
|
|
begin
|
102 |
|
|
if (pclk'event and pclk = '1') then
|
103 |
|
|
nVen <= not ctrl_Ven;
|
104 |
|
|
end if;
|
105 |
|
|
end process sync_settings;
|
106 |
|
|
|
107 |
|
|
-- hookup video timing generator
|
108 |
|
|
vtgen: tgen port map (clk => pclk, rst => nVen, HSyncL => ctrl_HSyncL, Thsync => Thsync, Thgdel => Thgdel, Thgate => Thgate, Thlen => Thlen,
|
109 |
|
|
VsyncL => ctrl_VsyncL, Tvsync => Tvsync, Tvgdel => Tvgdel, Tvgate => Tvgate, Tvlen => Tvlen, CSyncL => ctrl_CSyncL,
|
110 |
|
|
BlankL => ctrl_BlankL, eol => eol, eof => eof, gate => gate, Hsync => Hsync, Vsync => Vsync, Csync => Csync, Blank => Blank);
|
111 |
|
|
end block tblk;
|
112 |
|
|
|
113 |
|
|
--
|
114 |
|
|
-- pixel clock
|
115 |
|
|
--
|
116 |
|
|
pblk: block
|
117 |
|
|
signal seol, seof : std_logic; -- synchronized end-of-line, end-of-frame
|
118 |
|
|
signal dseol, dseof : std_logic; -- delayed synchronized eol, eof
|
119 |
|
|
begin
|
120 |
|
|
-- synchronize eol, eof (from pixel-clock-domain to master-clock-domain)
|
121 |
|
|
sync_eol_eof: process(mclk)
|
122 |
|
|
begin
|
123 |
|
|
if (mclk'event and mclk = '1') then
|
124 |
|
|
seol <= eol;
|
125 |
|
|
dseol <= seol;
|
126 |
|
|
seof <= eof;
|
127 |
|
|
dseof <= seof;
|
128 |
|
|
eoh <= seol and not dseol;
|
129 |
|
|
eov <= seof and not dseof;
|
130 |
|
|
end if;
|
131 |
|
|
end process sync_eol_eof;
|
132 |
|
|
end block pblk;
|
133 |
|
|
|
134 |
|
|
end architecture dataflow;
|