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[/] [vga_lcd/] [trunk/] [rtl/] [vhdl/] [vga_and_clut_tstbench.vhd] - Blame information for rev 62

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1 16 rudi
--
2
-- file: vga_and_clut_tstbench.vhd
3
-- project: VGA/LCD controller + Color Lookup Table
4
-- author: Richard Herveille
5
--
6
-- Testbench for VGA controller + CLUT combination
7
--
8
-- rev 1.0 July 4th, 2001.
9
--
10
 
11
library ieee;
12
use ieee.std_logic_1164.all;
13
use ieee.std_logic_arith.all;
14
 
15
entity tst_bench is
16
end entity tst_bench;
17
 
18
architecture test of tst_bench is
19
        --
20
        -- component declarations
21
        --
22
 
23
        component vga_and_clut is
24
        port(
25
                CLK_I   : in std_logic;                         -- wishbone clock input
26
                RST_I   : in std_logic;                         -- synchronous active high reset
27
                NRESET  : in std_logic := '1';                  -- asynchronous active low reset
28
                INTA_O  : out std_logic;                        -- interrupt request output
29
 
30
                -- slave signals
31
                ADR_I      : in unsigned(10 downto 2);          -- addressbus input (only 32bit databus accesses supported)
32
                SDAT_I     : in std_logic_vector(31 downto 0);  -- Slave databus output
33
                SDAT_O     : out std_logic_vector(31 downto 0); -- Slave databus input
34
                SEL_I      : in std_logic_vector(3 downto 0);   -- byte select inputs
35
                WE_I       : in std_logic;                      -- write enabel input
36
                VGA_STB_I  : in std_logic;                      -- vga strobe/select input
37
                CLUT_STB_I : in std_logic;                      -- color-lookup-table strobe/select input
38
                CYC_I      : in std_logic;                      -- valid bus cycle input
39
                ACK_O      : out std_logic;                     -- bus cycle acknowledge output
40
                ERR_O      : out std_logic;                     -- bus cycle error output
41
 
42
                -- master signals
43
                ADR_O : out unsigned(31 downto 2);              -- addressbus output
44
                MDAT_I : in std_logic_vector(31 downto 0);      -- Master databus input
45
                SEL_O : out std_logic_vector(3 downto 0);       -- byte select outputs
46
                WE_O : out std_logic;                           -- write enable output
47
                STB_O : out std_logic;                          -- strobe output
48
                CYC_O : out std_logic;                          -- valid bus cycle output
49
                CAB_O : out std_logic;                          -- continuos address burst output
50
                ACK_I : in std_logic;                           -- bus cycle acknowledge input
51
                ERR_I : in std_logic;                           -- bus cycle error input
52
 
53
                -- VGA signals
54
                PCLK : in std_logic;                            -- pixel clock
55
                HSYNC : out std_logic;                          -- horizontal sync
56
                VSYNC : out std_logic;                          -- vertical sync
57
                CSYNC : out std_logic;                          -- composite sync
58
                BLANK : out std_logic;                          -- blanking signal
59
                R,G,B : out std_logic_vector(7 downto 0)        -- RGB color signals
60
        );
61
        end component vga_and_clut;
62
 
63
        component wb_host is
64
        generic(
65
                RST_LVL : std_logic := '0'                -- reset level
66
        );
67
        port(
68
                clk_i : in std_logic;
69
                rst_i : in std_logic;
70
 
71
                cyc_o : out std_logic;
72
                stb_o : out std_logic;
73
                we_o  : out std_logic;
74
                adr_o : out std_logic_vector(31 downto 0);
75
                dat_o : out std_logic_vector(31 downto 0);
76
                dat_i : in std_logic_vector(31 downto 0);
77
                sel_o : out std_logic_vector(3 downto 0);
78
                ack_i : in std_logic;
79
                err_i : in std_logic
80
        );
81
        end component wb_host;
82
 
83
        component vid_mem is
84
        generic(
85
                ACK_DELAY : natural := 2
86
        );
87
        port(
88
                clk_i : in std_logic;
89
                adr_i : in unsigned (15 downto 0);
90
                cyc_i : in std_logic;
91
                stb_i : in std_logic;
92
                dat_o : out std_logic_vector(31 downto 0);
93
                ack_o : out std_logic
94
        );
95
        end component vid_mem;
96
 
97
        --
98
        -- signal declarations
99
        --
100
 
101
        -- clock & reset
102
        signal clk, vga_clk : std_logic := '0';
103
        signal rst : std_logic := '1';
104
        signal init : std_logic := '0';
105
 
106
        -- wishbone host
107
        signal h_cyc_o, h_stb_o, h_we_o : std_logic;
108
        signal h_adr_o                  : unsigned(31 downto 0);
109
        signal h_dat_o, h_dat_i         : std_logic_vector(31 downto 0);
110
        signal h_sel_o                  : std_logic_vector(3 downto 0);
111
        signal h_ack_i, h_err_i         : std_logic;
112
 
113
        -- vga master
114
        signal vga_adr_o                       : unsigned(31 downto 2);
115
        signal vga_dat_i                       : std_logic_vector(31 downto 0);
116
        signal vga_stb_o, vga_cyc_o, vga_ack_i : std_logic;
117
        signal vga_sel_o                       : std_logic_vector(3 downto 0);
118
        signal vga_we_o, vga_err_i             : std_logic;
119
 
120
        -- vga
121
        signal r, g, b : std_logic_vector(7 downto 0);
122
        signal hsync, vsync, csync, blank : std_logic;
123
begin
124
 
125
        -- generate clocks
126
        clk_block: block
127
        begin
128
                process(clk)
129
                begin
130
                        clk <= not clk after 2.5 ns; -- 200MHz wishbone clock
131
                end process;
132
 
133
                process(vga_clk)
134
                begin
135
                        vga_clk <= not vga_clk after 12.5 ns; -- 40MHz vga clock
136
                end process;
137
        end block clk_block;
138
 
139
        -- generate reset signal
140
        gen_rst: process(init, rst)
141
        begin
142
                if (init = '0') then
143
                        rst <= '0' after 100 ns;
144
                        init <= '1';
145
                end if;
146
        end process gen_rst;
147
 
148
        --
149
        -- hookup vga + clut core
150
        --
151
        u1: vga_and_clut port map (CLK_I => clk, RST_I => RST, ADR_I => h_adr_o(10 downto 2),
152
                SDAT_I => h_dat_o, SDAT_O => h_dat_i, SEL_I => h_sel_o, WE_I => h_we_o, VGA_STB_I => h_adr_o(31),
153
                CLUT_STB_I => h_adr_o(30), CYC_I => h_cyc_o, ACK_O => h_ack_i, ERR_O => h_err_i,
154
                ADR_O => vga_adr_o, MDAT_I => vga_dat_i, SEL_O => vga_sel_o, WE_O => vga_we_o, STB_O => vga_stb_o,
155
                CYC_O => vga_cyc_o, ACK_I => vga_ack_i, ERR_I => vga_err_i,
156
                PCLK => vga_clk, HSYNC => hsync, VSYNC => vsync, CSYNC => csync, BLANK => blank, R => r, G => g, B => b);
157
 
158
        --
159
        -- hookup wishbone host
160
        --
161
        u2: wb_host
162
                generic map (RST_LVL => '1')
163
                port map (clk_i => clk, rst_i => rst, cyc_o => h_cyc_o, stb_o => h_stb_o, we_o => h_we_o, unsigned(adr_o) => h_adr_o,
164
                        dat_o => h_dat_o, dat_i => h_dat_i, sel_o => h_sel_o, ack_i => h_ack_i, err_i => h_err_i);
165
 
166
        u3: vid_mem
167
                        generic map (ACK_DELAY => 0)
168
                        port map (clk_i => clk, adr_i => vga_adr_o(17 downto 2), cyc_i => vga_cyc_o,
169
                                stb_i => vga_stb_o, dat_o => vga_dat_i, ack_o => vga_ack_i);
170
end architecture test;
171
 
172
--
173
------------------------------------
174
-- Wishbone host behavioral model --
175
------------------------------------
176
--
177
library ieee;
178
use ieee.std_logic_1164.all;
179
use ieee.std_logic_arith.all;
180
library std;
181
use std.standard.all;
182
 
183
entity wb_host is
184
        generic(
185
                RST_LVL : std_logic := '1'                -- reset level
186
        );
187
        port(
188
                clk_i : in std_logic;
189
                rst_i : in std_logic;
190
 
191
                cyc_o : out std_logic;
192
                stb_o : out std_logic;
193
                we_o  : out std_logic;
194
                adr_o : out std_logic_vector(31 downto 0);
195
                dat_o : out std_logic_vector(31 downto 0);
196
                dat_i : in std_logic_vector(31 downto 0);
197
                sel_o : out std_logic_vector(3 downto 0);
198
                ack_i : in std_logic;
199
                err_i : in std_logic
200
        );
201
end entity wb_host;
202
 
203
architecture behavioral of wb_host is
204
        -- type declarations
205
        type vector_type is
206
                record
207
                        adr   : std_logic_vector(31 downto 0); -- wishbone address output
208
                        we    : std_logic;                     -- wishbone write enable output
209
                        dat   : std_logic_vector(31 downto 0); -- wishbone data output (write) or input compare value (read)
210
                        sel   : std_logic_vector(3 downto 0);  -- wishbone byte select output
211
                        stop  : std_logic;                     -- last field, stop wishbone activities
212
                end record;
213
 
214
        type vector_list is array(0 to 38) of vector_type;
215
 
216
        type states is (chk_stop, gen_cycle);
217
 
218
        -- signal declarations
219
        signal state : states;
220
        signal cnt : natural := 0;
221
        signal cyc, stb : std_logic;
222
 
223
        shared variable vectors : vector_list :=
224
                (
225
                        -- fill clut (adr(30) = '1')
226
                        (x"40000000",'1',x"00123456","1111",'0'), --0
227
                        (x"40000004",'1',x"00789abc","1111",'0'),
228
                        (x"40000008",'1',x"00def010","1111",'0'),
229
                        (x"4000000C",'1',x"00010203","1111",'0'),
230
                        (x"40000010",'1',x"00040506","1111",'0'),
231
                        (x"40000014",'1',x"00070809","1111",'0'),
232
                        (x"40000018",'1',x"000a0b0c","1111",'0'),
233
                        (x"4000001C",'1',x"00102030","1111",'0'),
234
                        (x"40000020",'1',x"00405060","1111",'0'),
235
                        (x"40000024",'1',x"00708090","1111",'0'),
236
                        (x"40000028",'1',x"00a0b0c0","1111",'0'),
237
                        (x"4000002C",'1',x"00112233","1111",'0'),
238
                        (x"40000030",'1',x"00445566","1111",'0'),
239
                        (x"40000034",'1',x"00778899","1111",'0'),
240
                        (x"40000038",'1',x"00aabbcc","1111",'0'),
241
                        (x"4000003C",'1',x"00ddeeff","1111",'0'),
242
 
243
                        -- verify data written
244
                        (x"40000000",'0',x"00123456","1111",'0'), --16
245
                        (x"40000004",'0',x"00789abc","1111",'0'),
246
                        (x"40000008",'0',x"00def010","1111",'0'),
247
                        (x"4000000C",'0',x"00010203","1111",'0'),
248
                        (x"40000010",'0',x"00040506","1111",'0'),
249
                        (x"40000014",'0',x"00070809","1111",'0'),
250
                        (x"40000018",'0',x"000a0b0c","1111",'0'),
251
                        (x"4000001C",'0',x"00102030","1111",'0'),
252
                        (x"40000020",'0',x"00405060","1111",'0'),
253
                        (x"40000024",'0',x"00708090","1111",'0'),
254
                        (x"40000028",'0',x"00a0b0c0","1111",'0'),
255
                        (x"4000002C",'0',x"00112233","1111",'0'),
256
                        (x"40000030",'0',x"00445566","1111",'0'),
257
                        (x"40000034",'0',x"00778899","1111",'0'),
258
                        (x"40000038",'0',x"00aabbcc","1111",'0'),
259
                        (x"4000003C",'0',x"00ddeeff","1111",'0'),
260
 
261
                        -- program vga controller
262
                        (x"80000008",'1',x"04090018","1111",'0'), --32 program horizontal timing register (25 visible pixels per line)
263
                        (x"8000000c",'1',x"05010003","1111",'0'), --   program vertical timing register (4 visible lines per frame)
264
                        (x"80000010",'1',x"00320016","1111",'0'), --   program horizontal/vertical length register (50x50 pixels)
265
                        (x"80000014",'1',x"10000000","1111",'0'), --   program video base address 0 register (sdram)
266
                        (x"8000001c",'1',x"10200000","1111",'0'), --   program color lookup table (sram)
267
                        (x"80000000",'1',x"00000901","1111",'0'), --   program control register (enable video system)
268
 
269
                        -- end list
270
                        (x"00000000",'0',x"00000000","1111",'1')  --38 stop testbench
271
                );
272
 
273
begin
274
        process(clk_i, cnt, ack_i, err_i)
275
                variable nxt_state : states;
276
                variable icnt : natural;
277
        begin
278
 
279
                nxt_state := state;
280
                icnt := cnt;
281
 
282
                case state is
283
                        when chk_stop =>
284
                                cyc <= '0';                          -- no valid bus-cycle
285
                                stb <= '0';                          -- disable strobe output
286
                                if (vectors(cnt).stop = '0') then
287
                                        nxt_state := gen_cycle;
288
                                        cyc <= '1';
289
                                        stb <= '1';
290
                                end if;
291
 
292
                        when gen_cycle =>
293
                                cyc <= '1';
294
                                stb <= '1';
295
                                if (ack_i = '1') or (err_i = '1') then
296
                                        nxt_state := chk_stop;
297
                                        cyc <= '0';
298
                                        stb <= '0';
299
 
300
                                        icnt := cnt +1;
301
 
302
                                        --
303
                                        -- check assertion of ERR_I
304
                                        --
305
                                        if (err_i = '1') then
306
                                                if (clk_i'event and clk_i = '1') then -- display warning only at rising edge of clock
307
--                                                      report ("ERR_I asserted at vectorno. ")& cnt 
308
--                                                                      severity warning;
309
                                                        report ("ERR_I asserted at vectorno. ") severity error;
310
                                                end if;
311
                                        end if;
312
 
313
                                        --
314
                                        -- compare DAT_I with expected data during ACK_I assertion
315
                                        --
316
                                        if (vectors(cnt).we = '0') then
317
                                                if (vectors(cnt).dat /= dat_i) then
318
                                                        if (clk_i'event and clk_i = '1') then -- display warning only at rising edge of clock
319
--                                                              report ("DAT_I not equal to compare value. Expected ")& vectors(cnt).dat_i & (" received ") & dat_i;
320
--                                                                       severity warning;
321
                                                                report ("DAT_I not equal to compare value") severity error;
322
                                                        end if;
323
                                                end if;
324
                                        end if;
325
 
326
                                end if;
327
                end case;
328
 
329
 
330
                if (clk_i'event and clk_i = '1') then
331
                        if (rst_i = RST_LVL) then
332
                                state <= chk_stop;
333
                                cyc_o <= '0';
334
                                stb_o <= '0';
335
                                adr_o <= (others => 'X');
336
                                dat_o <= (others => 'X');
337
                                we_o  <= 'X';
338
                                sel_o <= (others => 'X');
339
                        else
340
                                state <= nxt_state;
341
                                cyc_o <= cyc;
342
                                stb_o <= stb;
343
 
344
                                if (cyc = '1') then
345
                                        adr_o <= vectors(cnt).adr;
346
                                        dat_o <= vectors(cnt).dat;
347
                                        we_o  <= vectors(cnt).we;
348
                                        sel_o <= vectors(cnt).sel;
349
                                else
350
                                        adr_o <= (others => 'X');
351
                                        dat_o <= (others => 'X');
352
                                        we_o  <= 'X';
353
                                        sel_o <= (others => 'X');
354
                                end if;
355
                        end if;
356
 
357
                        cnt <= icnt;
358
                end if;
359
        end process;
360
end architecture behavioral;
361
 
362
--
363
------------------------
364
-- video memory (ROM) --
365
------------------------
366
--
367
library ieee;
368
use ieee.std_logic_1164.all;
369
use ieee.std_logic_arith.all;
370
 
371
entity vid_mem is
372
        generic(
373
                ACK_DELAY : natural := 2
374
        );
375
        port(
376
                clk_i : in std_logic;
377
                adr_i : in unsigned (15 downto 0);
378
                cyc_i : in std_logic;
379
                stb_i : in std_logic;
380
                dat_o : out std_logic_vector(31 downto 0);
381
                ack_o : out std_logic
382
        );
383
end entity vid_mem;
384
 
385
architecture behavioral of vid_mem is
386
        signal cnt : unsigned(2 downto 0) := conv_unsigned(ACK_DELAY, 3);
387
        signal my_ack : std_logic;
388
begin
389
        with adr_i(15 downto 0) select
390
                dat_o <= x"01020304" when x"0000",
391
                         x"05060708" when x"0001",
392
                         x"090a0b0c" when x"0002",
393
                         x"0d0e0f00" when x"0003",
394
              x"a5a5a5a5" when others;
395
 
396
                gen_ack: process(clk_i)
397
                begin
398
                        if (clk_i'event and clk_i = '1') then
399
                                if (my_ack = '1') then
400
                                        cnt <= conv_unsigned(ACK_DELAY, 3);
401
                                elsif ((cyc_i = '1') and (stb_i = '1')) then
402
                                        cnt <= cnt -1;
403
                                end if;
404
                        end if;
405
                end process gen_ack;
406
 
407
                my_ack <= '1' when ((cyc_i = '1') and (stb_i = '1') and (cnt = 0)) else '0';
408
                ack_o <= my_ack;
409
end architecture behavioral;
410
 
411
 
412
 
413
 
414
 
415
 

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