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[/] [vga_lcd/] [trunk/] [rtl/] [vhdl/] [vtim.vhd] - Blame information for rev 16

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--
-- File vtim.vhd, Video Timing Generator
-- Project: VGA
-- Author : Richard Herveille
-- rev.: 0.1 April 13th, 2001
-- rev.: 0.2 June  23nd, 2001. Removed unused "rst_strb" signal.
-- rev.: 0.3 June  29th, 2001. Changed 'gen_go' process to use clock-enable signal.
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
library count;
use count.count.all;
 
entity vtim is
        port(
                clk : in std_logic;                -- master clock
                ena : in std_logic;                -- count enable
                rst : in std_logic;                -- synchronous active high reset
 
                Tsync : in unsigned(7 downto 0);   -- sync duration
                Tgdel : in unsigned(7 downto 0);   -- gate delay
                Tgate : in unsigned(15 downto 0);  -- gate length
                Tlen  : in unsigned(15 downto 0);  -- line time / frame time
 
                Sync  : out std_logic;             -- synchronization pulse
                Gate  : out std_logic;             -- gate
                Done  : out std_logic              -- done with line/frame
        );
end entity vtim;
 
architecture structural of vtim is
        signal Dsync, Dgdel, Dgate, Dlen : std_logic;
        signal go, drst : std_logic;
begin
        -- generate go signal
        gen_go: process(clk)
        begin
                if (clk'event and clk = '1') then
                        if (rst = '1') then
                                go <= '0';
                                drst <= '1';
                        elsif (ena = '1') then
                                go <= Dlen or (not rst and drst);
                                drst <= rst;
                        end if;
                end if;
        end process gen_go;
--      go <= Dlen or (not rst and drst); does not work => horizontal Dlen counter does not reload
 
        -- hookup sync counter
        sync_cnt : ro_cnt generic map (SIZE => 8)
                port map (clk => clk, rst => rst, cnt_en => ena, go => go, D => Tsync, iD => Tsync, done => Dsync);
 
        -- hookup gate delay counter
        gdel_cnt : ro_cnt generic map (SIZE => 8)
                port map (clk => clk, rst => rst, cnt_en => ena, go => Dsync, D => Tgdel, iD => Tgdel, done => Dgdel);
 
        -- hookup gate counter
        gate_cnt : ro_cnt generic map (SIZE => 16)
                port map (clk => clk, rst => rst, cnt_en => ena, go => Dgdel, D => Tgate, iD => Tgate, done => Dgate);
 
        -- hookup gate counter
        len_cnt : ro_cnt generic map (SIZE => 16)
                port map (clk => clk, rst => rst, cnt_en => ena, go => go, D => Tlen, iD => Tlen, done => Dlen);
 
        -- generate output signals
        gen_sync: block
                signal iSync : std_logic;
        begin
                process(clk)
                begin
                        if (clk'event and clk = '1') then
                                if (rst = '1') then
                                        iSync <= '0';
                                else
                                        iSync <= (go or iSync) and not Dsync;
                                end if;
                        end if;
                end process;
                Sync <= iSync;
        end block gen_sync;
 
        gen_gate: block
                signal iGate : std_logic;
        begin
                process(clk)
                begin
                        if (clk'event and clk = '1') then
                                if (rst = '1') then
                                        iGate <= '0';
                                else
                                        iGate <= (Dgdel or iGate) and not Dgate;
                                end if;
                        end if;
                end process;
 
                Gate <= iGate;
        end block gen_gate;
 
        Done <= Dlen;
end architecture structural;
 
 
 

Line No.	Rev	Author	Line
1	16	rudi	`--`
2			`-- File vtim.vhd, Video Timing Generator`
3			`-- Project: VGA`
4			`-- Author : Richard Herveille`
5			`-- rev.: 0.1 April 13th, 2001`
6			`-- rev.: 0.2 June 23nd, 2001. Removed unused "rst_strb" signal.`
7			`-- rev.: 0.3 June 29th, 2001. Changed 'gen_go' process to use clock-enable signal.`
8			`--`
9
10			`library ieee;`
11			`use ieee.std_logic_1164.all;`
12			`use ieee.std_logic_arith.all;`
13
14			`library count;`
15			`use count.count.all;`
16
17			`entity vtim is`
18			`port(`
19			`clk : in std_logic; -- master clock`
20			`ena : in std_logic; -- count enable`
21			`rst : in std_logic; -- synchronous active high reset`
22
23			`Tsync : in unsigned(7 downto 0); -- sync duration`
24			`Tgdel : in unsigned(7 downto 0); -- gate delay`
25			`Tgate : in unsigned(15 downto 0); -- gate length`
26			`Tlen : in unsigned(15 downto 0); -- line time / frame time`
27
28			`Sync : out std_logic; -- synchronization pulse`
29			`Gate : out std_logic; -- gate`
30			`Done : out std_logic -- done with line/frame`
31			`);`
32			`end entity vtim;`
33
34			`architecture structural of vtim is`
35			`signal Dsync, Dgdel, Dgate, Dlen : std_logic;`
36			`signal go, drst : std_logic;`
37			`begin`
38			`-- generate go signal`
39			`gen_go: process(clk)`
40			`begin`
41			`if (clk'event and clk = '1') then`
42			`if (rst = '1') then`
43			`go <= '0';`
44			`drst <= '1';`
45			`elsif (ena = '1') then`
46			`go <= Dlen or (not rst and drst);`
47			`drst <= rst;`
48			`end if;`
49			`end if;`
50			`end process gen_go;`
51			`-- go <= Dlen or (not rst and drst); does not work => horizontal Dlen counter does not reload`
52
53			`-- hookup sync counter`
54			`sync_cnt : ro_cnt generic map (SIZE => 8)`
55			`port map (clk => clk, rst => rst, cnt_en => ena, go => go, D => Tsync, iD => Tsync, done => Dsync);`
56
57			`-- hookup gate delay counter`
58			`gdel_cnt : ro_cnt generic map (SIZE => 8)`
59			`port map (clk => clk, rst => rst, cnt_en => ena, go => Dsync, D => Tgdel, iD => Tgdel, done => Dgdel);`
60
61			`-- hookup gate counter`
62			`gate_cnt : ro_cnt generic map (SIZE => 16)`
63			`port map (clk => clk, rst => rst, cnt_en => ena, go => Dgdel, D => Tgate, iD => Tgate, done => Dgate);`
64
65			`-- hookup gate counter`
66			`len_cnt : ro_cnt generic map (SIZE => 16)`
67			`port map (clk => clk, rst => rst, cnt_en => ena, go => go, D => Tlen, iD => Tlen, done => Dlen);`
68
69			`-- generate output signals`
70			`gen_sync: block`
71			`signal iSync : std_logic;`
72			`begin`
73			`process(clk)`
74			`begin`
75			`if (clk'event and clk = '1') then`
76			`if (rst = '1') then`
77			`iSync <= '0';`
78			`else`
79			`iSync <= (go or iSync) and not Dsync;`
80			`end if;`
81			`end if;`
82			`end process;`
83			`Sync <= iSync;`
84			`end block gen_sync;`
85
86			`gen_gate: block`
87			`signal iGate : std_logic;`
88			`begin`
89			`process(clk)`
90			`begin`
91			`if (clk'event and clk = '1') then`
92			`if (rst = '1') then`
93			`iGate <= '0';`
94			`else`
95			`iGate <= (Dgdel or iGate) and not Dgate;`
96			`end if;`
97			`end if;`
98			`end process;`
99
100			`Gate <= iGate;`
101			`end block gen_gate;`
102
103			`Done <= Dlen;`
104			`end architecture structural;`
105
106
107

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[/] [vga_lcd/] [trunk/] [rtl/] [vhdl/] [vtim.vhd] - Blame information for rev 16