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rherveille |
/*
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Include file for OpenCores VGA/LCD Controller ////
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//// ////
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//// File : oc_vga_lcd.h ////
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//// Function: c-include file ////
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//// ////
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//// Authors: Richard Herveille (richard@asics.ws) ////
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//// www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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*/
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/*
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* Definitions for the Opencores VGA/LCD Controller Core
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*/
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/* --- Register definitions --- */
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/* ----- Read-write access */
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#define OC_VGA_CTRL 0x000 /* Control register */
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#define OC_VGA_STAT 0x004 /* Status register */
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#define OC_VGA_HTIM 0x008 /* Horizontal Timing register */
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#define OC_VGA_VTIM 0x00c /* Vertical Timing register */
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#define OC_VGA_HVLEN 0x010 /* Horizontal/Vertical length register*/
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#define OC_VGA_VBARA 0x014 /* Video Base Address register A */
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#define OC_VGA_VBARB 0x018 /* Video Base Address register B */
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/* ----- Bits definition */
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/* ----- Control register */
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/* bits 31-16 are reserved */
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#define OC_VGA_BL (1<<15) /* Blank level bit: */
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#define OC_VGA_CSL (1<<14) /* Composite Sync. level bit */
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#define OC_VGA_VSL (1<<13) /* Vertical Sync. level bit */
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#define OC_VGA_HSL (1<<12) /* Horizontal Sync. level bit */
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/* 0 - Positive */
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/* 1 - Negative */
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#define OC_VGA_PC (1<<11) /* Pseudo Color (only for 8bpp mode) */
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/* 0 - 8bpp gray scale */
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/* 1 - 8bpp pseudo color */
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#define OC_VGA_CD (1<< 9) /* Color Depth */
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/* 00 - 8bits per pixel */
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/* 01 - 16bits per pixel */
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/* 10 - 24bits per pixel */
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/* 11 - reserved */
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#define OC_VGA_VBL (1<< 7) /* Video burst length */
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/* 00 - 1 cycle */
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/* 01 - 2 cycle */
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/* 10 - 4 cycle */
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/* 11 - 8 cycle */
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#define OC_VGA_CBSWE (1<<6) /* CLUT Bank Switch Enable bit */
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#define OC_VGA_VBSWE (1<<5) /* Video Bank Switch Enable bit */
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#define OC_VGA_CBSIE (1<<4) /* CLUT Bank Switch Interrupt enable */
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#define OC_VGA_VBSIE (1<<3) /* Video Bank Switch Interrupt enable */
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#define OC_VGA_HIE (1<<2) /* Horizontal Interrupt enable */
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#define OC_VGA_VIE (1<<1) /* Vertical Interrupt enable */
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#define OC_VGA_VEN (1<<0) /* Video Enable bit */
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/* 1 - Enabled */
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/* 0 - Disabled */
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/* ----- Status register */
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/* bits 31-18 are reserved */
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#define OC_VGA_ACMP (1<<17) /* Active CLUT Memory Page */
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#define OC_VGA_AVMP (1<<16) /* Active Video Memory Page */
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/* bits 15-8 are reserved */
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#define OC_VGA_CBSINT (1<<7) /* CLUT Bank Switch Interrupt pending */
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#define OC_VGA_VBSINT (1<<6) /* Bank Switch Interrupt pending */
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#define OC_VGA_HINT (1<<5) /* Horizontal Interrupt pending */
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#define OC_VGA_VINT (1<<4) /* Vertical Interrupt pending */
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/* bits 3-2 are reserved */
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#define OC_VGA_LUINT (1<<1) /* LineFIFO Underrun interrupt pending*/
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#define OC_VGA_SINT (1<<0) /* System Error Interrupt pending */
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/* ----- Horizontal/Vertical Timing registers */
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#define OC_VGA_TSYNC (1<<24) /* Synchronization pulse width */
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#define OC_VGA_TGDEL (1<<16) /* Gate delay time */
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#define OC_VGA_TGATE (1<< 0) /* Gate time */
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/* ----- Horizontal and Vertcial Length registers */
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#define OC_VGA_THLEN (1<<16) /* Horizontal length */
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#define OC_VGA_TVLEN (1<< 0) /* Vertical length */
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/* bit testing and setting macros */
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#define OC_ISSET(reg,bitmask) ((reg)&(bitmask))
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#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask)))
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#define OC_BITSET(reg,bitmask) ((reg)|(bitmask))
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#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask)))
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#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask))
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#define OC_REGMOVE(reg,value) ((reg)=(value))
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