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droggen |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.std_logic_unsigned.ALL;
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entity hexto7seg is
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port(
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clk: in std_logic;
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d7: in std_logic_vector(3 downto 0);
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d6: in std_logic_vector(3 downto 0);
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d5: in std_logic_vector(3 downto 0);
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d4: in std_logic_vector(3 downto 0);
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d3: in std_logic_vector(3 downto 0);
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d2: in std_logic_vector(3 downto 0);
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d1: in std_logic_vector(3 downto 0);
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d0: in std_logic_vector(3 downto 0);
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blink: in std_logic_vector(7 downto 0);
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q: out std_logic_vector(6 downto 0);
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active : out std_logic_vector(7 downto 0)
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);
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end hexto7seg;
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architecture Behavioral of hexto7seg is
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signal a: std_logic;
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signal b: std_logic;
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signal c: std_logic;
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signal d: std_logic;
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signal qt: std_logic_vector(6 downto 0);
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signal ctr: std_logic_vector(2 downto 0);
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signal divider: std_logic_vector(25 downto 0);
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begin
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p1: process(clk)
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begin
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if rising_edge(clk) then
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divider<=divider+1;
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end if;
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end process;
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p2: process(clk)
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begin
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if rising_edge(clk) then
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if divider(9 downto 0)="0000000000" then
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ctr<=ctr+1;
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end if;
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end if;
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end process;
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-- input mux
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with ctr select
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a <= d0(3) when "000",
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d1(3) when "001",
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d2(3) when "010",
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d3(3) when "011",
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d4(3) when "100",
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d5(3) when "101",
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d6(3) when "110",
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d7(3) when others;
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with ctr select
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b <= d0(2) when "000",
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d1(2) when "001",
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d2(2) when "010",
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d3(2) when "011",
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d4(2) when "100",
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d5(2) when "101",
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d6(2) when "110",
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d7(2) when others;
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with ctr select
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c <= d0(1) when "000",
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d1(1) when "001",
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d2(1) when "010",
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d3(1) when "011",
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d4(1) when "100",
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d5(1) when "101",
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d6(1) when "110",
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d7(1) when others;
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with ctr select
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d <= d0(0) when "000",
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d1(0) when "001",
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d2(0) when "010",
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d3(0) when "011",
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d4(0) when "100",
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d5(0) when "101",
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d6(0) when "110",
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d7(0) when others;
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-- Output mux
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with ctr select
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active <= "11111110" when "000",
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"11111101" when "001",
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"11111011" when "010",
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"11110111" when "011",
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"11101111" when "100",
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"11011111" when "101",
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"10111111" when "110",
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"01111111" when others;
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-- Blinking
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q(0) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(0);
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q(1) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(1);
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q(2) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(2);
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q(3) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(3);
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q(4) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(4);
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q(5) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(5);
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q(6) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(6);
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qt(0) <= not ( (not a and not b and not c and not d )
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or (not a and not b and c and not d)
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or (not a and not b and c and d)
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or (not a and b and not c and d)
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or (not a and b and c and not d)
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or (not a and b and c and d)
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or (a and not b and not c and not d)
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or (a and not b and not c and d)
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or (a and not b and c and not d)
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or (a and b and not c and not d)
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or (a and b and c and not d)
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or (a and b and c and d) );
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qt(1) <= not ( (not a and not b and not c and not d)
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or (not a and not b and not c and d)
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or (not a and not b and c and not d)
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or (not a and not b and c and c)
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or (not a and b and not c and not d)
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or (not a and b and c and d)
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or (a and not b and not c and not d)
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or (a and not b and not c and d)
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or (a and not b and c and not d)
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or (a and b and not c and d) );
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qt(2) <= not ( (not a and not b and not c and not d)
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or (not a and not b and not c and d)
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or (not a and not b and c and d)
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or (not a and b and not c and not d)
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or (not a and b and not c and d)
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or (not a and b and c and not d)
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or (not a and b and c and d)
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or (a and not b and not c and not d)
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or (a and not b and not c and d)
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or (a and not b and c and not d)
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or (a and not b and c and d)
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or (a and b and not c and d) );
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qt(3) <= not ((not a and not b and not c and not d)
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or (not a and not b and c and not d)
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or (not a and not b and c and d)
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or (not a and b and not c and d)
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or (not a and b and c and not d)
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or (a and not b and not c and not d)
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or (a and not b and c and d)
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or (a and b and not c and not d)
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or (a and b and not c and d)
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or (a and b and c and not d) );
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--qt(4) <= not ((not a and not b and not c and not d)
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-- or (not a and not b and c and not d)
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-- or (not a and b and c and not d)
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-- or (a and not b and not c and not d)
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-- or (a and not b and c and not d)
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-- or (a and not b and c and d)
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-- or (a and b and not c and not d)
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-- or (a and b and not c and d)
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-- or (a and b and c and not d)
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-- or (a and b and c and d) );
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--qt(5) <= not ((not a and not b and not c and not d)
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-- or (not a and b and not c and not d)
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-- or (not a and b and not c and d)
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-- or (not a and b and c and not d)
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-- or (a and not b and not c and not d)
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-- or (a and not b and not c and d)
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-- or (a and not b and c and not d)
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-- or (a and not b and c and d)
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-- or (a and b and not c and not d)
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-- or (a and b and c and not d)
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-- or (a and b and c and d) );
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--qt(6) <= not ((not a and not b and c and not d)
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-- or (not a and not b and c and d)
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-- or (not a and b and not c and not d)
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-- or (not a and b and not c and d)
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-- or (not a and b and c and not d)
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-- or (a and not b and not c and not d)
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-- or (a and not b and not c and d)
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-- or (a and not b and c and not d)
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-- or (a and not b and c and d)
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-- or (a and b and not c and d)
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-- or (a and b and c and not d)
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-- or (a and b and c and d) );
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-- Minimized expression:
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qt(4) <= not( (a and b) or (a and c) or (c and not d) or (not b and not d) );
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qt(5) <= not( (b and not d) or (not a and b and not c) or (a and not b) or (a and c) or (not c and not d) );
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qt(6) <= not( (not a and b and not c) or (a and not b) or (a and d) or (not b and c and d) or (c and not d) );
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end Behavioral;
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