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Subversion Repositories vhdl_cpu_emulator

[/] [vhdl_cpu_emulator/] [trunk/] [thr_interrupt.txt] - Blame information for rev 3

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1 2 nachumk 
#set automatic transmit and receive for uart 0
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WRITE 00010000 00000011
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#unmask transmit ready and receive data for uart 0
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WRITE 00010100 11111100
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#set automatic transmit and receive for uart 1
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WRITE 00011000 00000011
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#unmask transmit ready and receive data for uart 1
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WRITE 00011100 11111100
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#clear global 0 for interrupts for uart 0
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int0shadow = 00000000
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#clear global 1 for interrupts for uart 1
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int1shadow = 00000000
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vector8 intshadow = 00000000
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WAIT 2 us
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WHILE
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        WAIT_INTERRUPT4
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        #read interrupt reg uart 0
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        READ 00010101 intshadow
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        IF intshadow & 11111111
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                WRITE 00010101 intshadow
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        IF_END
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        int0shadow |= intshadow
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        #read interrupt reg uart 1
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        READ 00011101 intshadow
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        IF intshadow & 11111111
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                WRITE 00011101 intshadow
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        IF_END
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        int1shadow |= intshadow
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WHILE_END

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