URL https://opencores.org/ocsvn/vhdl_cpu_emulator/vhdl_cpu_emulator/trunk

Subversion Repositories vhdl_cpu_emulator

[/] [vhdl_cpu_emulator/] [trunk/] [thr_tx_uart1.txt] - Blame information for rev 3

Details | Compare with Previous | View Log


#wait for interrupt thread to do initialization
PARAMETERS vector8 txstart
WAIT 30 ns
#counter is now set by parameter at thread creation
 
WHILE
 
        WAIT 3 us
 
        #check if transmit ready interrupt - from interrupt thread
        vector8 tmp = int1shadow
        tmp &= 00000001
        IF tmp == 00000001
        int1shadow &= 11111110
        WRITE 00011110 txstart
        #increment counter for transmit
        txstart += 00000001
        IF_END
 
WHILE_END

Line No.	Rev	Author	Line
1	2	nachumk	`#wait for interrupt thread to do initialization`
2			`PARAMETERS vector8 txstart`
3			`WAIT 30 ns`
4			`#counter is now set by parameter at thread creation`
5
6			`WHILE`
7
8			`WAIT 3 us`
9
10			`#check if transmit ready interrupt - from interrupt thread`
11			`vector8 tmp = int1shadow`
12			`tmp &= 00000001`
13			`IF tmp == 00000001`
14			`int1shadow &= 11111110`
15			`WRITE 00011110 txstart`
16			`#increment counter for transmit`
17			`txstart += 00000001`
18			`IF_END`
19
20			`WHILE_END`

Browse

Tools

Subversion Repositories vhdl_cpu_emulator

[/] [vhdl_cpu_emulator/] [trunk/] [thr_tx_uart1.txt] - Blame information for rev 3