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sinx |
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- This file contains the top of the test case module. ----
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---- It contains only an entity whereas the architecture is ----
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---- located in several tc_xxxx files. ----
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---- Every test case shall have its own tc_xxxx file. Every ----
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---- tc_xxxx file needs to be compiled into the work library and ----
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---- simulated independently. Use a script to run all tc_xxx ----
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---- files automatically. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Sinx, sinx@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- SVN information
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----
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sinx |
---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tc_top.vhd $
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---- $Revision: 14 $
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---- $Date: 2018-07-22 16:27:41 +0200 (Sun, 22 Jul 2018) $
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---- $Author: sinx $
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---- $Id: tc_top.vhd 14 2018-07-22 14:27:41Z sinx $
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4 |
sinx |
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.convert_pkg.all;
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use work.my_project_pkg.all;
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use work.wishbone_pkg.all;
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use work.wishbone_bfm_pkg.all;
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-- entity ------------------------------------------------------------
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entity tc_top is
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port (
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wb_o : out wishbone_bfm_master_out_t;
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wb_i : in wishbone_bfm_master_in_t
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);
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end entity tc_top;
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----------------------------------------------------------------------
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---- end of file ----
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----------------------------------------------------------------------
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