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sinx |
----------------------------------------------------------------------
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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sinx |
---- This file contains the one test sequence for the test bench.----
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---- Several test sequences shall be stored in several tc_xxxx ----
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---- files. This file contains the architecture for the tc_top ----
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---- enity, lcated in tc_top.vhd. ----
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sinx |
---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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sinx |
---- - Sinx, sinx@opencores.org ----
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sinx |
---- ----
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----------------------------------------------------------------------
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sinx |
---- SVN information
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----
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---- $URL: $
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---- $Revision: $
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---- $Date: $
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---- $Author: $
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---- $Id: $
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----------------------------------------------------------------------
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sinx |
---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.convert_pkg.all;
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use work.wishbone_pkg.all;
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use work.wishbone_bfm_pkg.all;
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use work.my_project_pkg.all;
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use work.tb_pkg.all;
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-- architecture ------------------------------------------------------
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4 |
sinx |
architecture tc_xxxx of tc_top is
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----------------------------------------------------------------------
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sinx |
-- local constant definitions
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4 |
sinx |
----------------------------------------------------------------------
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sinx |
begin
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4 |
sinx |
----------------------------------------------------------------------
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sinx |
tc_xxxx_proc : process
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begin
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4 |
sinx |
----------------------------------------------------------------------
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2 |
sinx |
-- standard signal initialization
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wb_o <= wb_bfm_master_out_idle_c;
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wait until wb_i.rst = '0';
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wait until rising_edge(wb_i.clk);
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wait until rising_edge(wb_i.clk);
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--
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wait for 400 ns;
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wait until rising_edge(wb_i.clk);
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--
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4 |
sinx |
----------------------------------------------------------------------
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sinx |
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report "-----------------------------------------------------------------";
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report "-- tc_xxxx: ADD_DESCRIPTION_HERE --";
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report "-----------------------------------------------------------------";
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--
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report "--configure stimulator";
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report "-----------------------------------------------------------------";
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wb_write(stimulator_register0_c , 0, wb_i, wb_o);
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report "--configure verifier";
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report "-----------------------------------------------------------------";
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wb_write(verifier_register0_c , 2, wb_i, wb_o);
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wb_write(verifier_register1_c , 16#2b#, wb_i, wb_o);
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report "--configuration done";
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report "-----------------------------------------------------------------";
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report "--starting stimulator";
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report "-----------------------------------------------------------------";
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wb_write(stimulator_register0_c , 3, wb_i, wb_o); -- shift '1' in
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wb_write(stimulator_register0_c , 1, wb_i, wb_o);
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wb_write(stimulator_register0_c , 2, wb_i, wb_o); -- shift '0' in
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wb_write(stimulator_register0_c , 0, wb_i, wb_o);
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wb_read (verifier_register2_c , 2, wb_i, wb_o);
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wb_write(stimulator_register0_c , 3, wb_i, wb_o); -- shift '1' in
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wb_write(stimulator_register0_c , 1, wb_i, wb_o);
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wb_read (verifier_register2_c , 5, wb_i, wb_o); -- reads correct
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report "-----------------------------------------------------------------";
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report "-----------------------------------------------------------------";
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report "-- All fine till here. Now we provoke error messages for illustration.";
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wb_read (verifier_register2_c , 6, wb_i, wb_o); -- provoke error (read value is 5)
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wb_read (verifier_register2_c , 6, wb_i, wb_o,0); -- provoke error (read value is 5)
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wb_read (verifier_register2_c , 6, wb_i, wb_o,1); -- provoke error (read value is 5)
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wb_read (verifier_register2_c , 6, wb_i, wb_o,2); -- provoke error (read value is 5)
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wb_read (verifier_register2_c , 6, wb_i, wb_o,2,"<TEXT>"); -- provoke error (read value is 5)
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wb_read (verifier_register2_c , 6, wb_i, wb_o,3,"",7); -- provoke error (read value is 5)
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wb_read (verifier_register2_c , 6, wb_i, wb_o,4); -- provoke error (read value is 5)
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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report "-----------------------------------------------------------------";
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report "--check results";
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report "-----------------------------------------------------------------";
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wait for 6 us;
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wait until rising_edge(wb_i.clk);
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wb_read (verifier_register2_c, 16#0000_0005#, wb_i, wb_o);
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wait for 1 us;
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4 |
sinx |
----------------------------------------------------------------------
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2 |
sinx |
report "-- tc_xxxx finished";
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4 |
sinx |
----------------------------------------------------------------------
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2 |
sinx |
--
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report "test case tc_xxxx completed successfully"; --severity failure;
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report "-----------------------------------------------------------------";
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report "-----------------------------------------------------------------";
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4 |
sinx |
wait for 100 ns;
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if (exit_simulator_at_tc_end_c/="1") then
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std.env.stop; -- pause simulation
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else
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std.env.finish; -- stop simulation
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end if;
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2 |
sinx |
end process tc_xxxx_proc;
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4 |
sinx |
----------------------------------------------------------------------
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2 |
sinx |
end tc_xxxx;
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4 |
sinx |
----------------------------------------------------------------------
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---- end of file ----
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----------------------------------------------------------------------
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