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sinx |
----------------------------------------------------------------------
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- This file contains the top functional module of the design ----
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---- under test. The top functional module will be enclosed by ----
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---- the top module for synthesis or the tb_top for simulation. ----
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---- The top module can contain some synthesis specific code, ----
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---- where the tb_top contains simulation specific code. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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sinx |
---- - Sinx, sinx@opencores.org ----
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sinx |
---- ----
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----------------------------------------------------------------------
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sinx |
---- SVN information
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----
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sinx |
---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/core_top.vhd $
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---- $Revision: 14 $
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---- $Date: 2018-07-22 16:27:41 +0200 (Sun, 22 Jul 2018) $
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---- $Author: sinx $
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---- $Id: core_top.vhd 14 2018-07-22 14:27:41Z sinx $
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sinx |
----------------------------------------------------------------------
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sinx |
---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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47 |
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.convert_pkg.all;
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use work.wishbone_pkg.all;
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-- entity ------------------------------------------------------------
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entity core_top is
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generic(
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5 |
sinx |
number_of_in_signals_g : natural := 1;
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number_of_out_signals_g : natural := 1
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2 |
sinx |
);
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port(
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clock_i : in std_logic;
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reset_i : in std_logic;
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sinx |
signals_i : in std_logic_vector(number_of_in_signals_g-1 downto 0);
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73 |
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signals_o : out std_logic_vector(number_of_out_signals_g-1 downto 0)
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2 |
sinx |
);
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75 |
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end core_top;
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76 |
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4 |
sinx |
-- architecture ------------------------------------------------------
|
78 |
2 |
sinx |
architecture rtl of core_top is
|
79 |
4 |
sinx |
------------------------------------------------------------------------------
|
80 |
2 |
sinx |
-- signal declaration
|
81 |
4 |
sinx |
------------------------------------------------------------------------------
|
82 |
5 |
sinx |
signal shift_register_r : std_logic_vector (number_of_out_signals_g-1 downto 0);
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83 |
2 |
sinx |
signal old_shift_clock_r : std_logic := '0';
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84 |
4 |
sinx |
------------------------------------------------------------------------------
|
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2 |
sinx |
begin
|
86 |
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------------------------------------------------------------------------------
|
87 |
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-- module instantiation
|
88 |
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------------------------------------------------------------------------------
|
89 |
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proc_shift_register : process (all)
|
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begin
|
91 |
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if (reset_i = '1' ) then
|
92 |
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shift_register_r <= (others => '0');
|
93 |
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elsif (rising_edge(clock_i)) then
|
94 |
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old_shift_clock_r <= signals_i(1);
|
95 |
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if (signals_i(1) = '1' AND old_shift_clock_r= '0') then
|
96 |
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shift_register_r <= shift_register_r(shift_register_r'left-1 downto 0) & signals_i(0);
|
97 |
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end if;
|
98 |
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end if;
|
99 |
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end process;
|
100 |
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------------------------------------------------------------------------------
|
101 |
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signals_o <= shift_register_r;
|
102 |
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------------------------------------------------------------------------------
|
103 |
4 |
sinx |
end rtl;
|
104 |
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----------------------------------------------------------------------
|
105 |
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|
---- end of file ----
|
106 |
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----------------------------------------------------------------------
|