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----------------------------------------------------------------------
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- This file contains the wishbone_pkg package and defines ----
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---- basic wishbone types. ----
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---- ----
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---- This file bases on the file wishbone_pkg.vhd located at ----
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---- https://github.com/twlostow/dsi-shield/blob/master/hdl/ip_cores/local/wishbone_pkg.vhd ---
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---- See this file also for the authors name. ----
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---- Its original file was licensed under LGPL 3.0 ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Sinx, sinx@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- SVN information
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----
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---- $URL: $
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---- $Revision: $
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---- $Date: $
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---- $Author: $
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---- $Id: $
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.my_project_pkg.all;
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-- package -----------------------------------------------------------
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package wishbone_pkg is
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subtype wishbone_address_t is std_logic_vector(wishbone_address_width_c-1 downto 0);
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subtype wishbone_data_t is std_logic_vector(wishbone_data_width_c-1 downto 0);
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subtype wishbone_byte_select_t is std_logic_vector((wishbone_address_width_c/8)-1 downto 0);
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--subtype wishbone_cycle_type_t is std_logic_vector(2 downto 0);
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--subtype wishbone_burst_type_t is std_logic_vector(1 downto 0);
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type wishbone_master_out_t is record
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-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
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clk : std_logic; -- clock [mandatory RULE 3.40]
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dat : wishbone_data_t; -- data []
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rst : std_logic; -- reset [mandatory RULE 3.40]
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tgd : wishbone_tag_data_t; -- data tag []
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-- 2.2.3 MASTER Signals
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adr : wishbone_address_t; -- address [optional]
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cyc : std_logic; -- cycle [mandatory RULE 3.40]
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lock: std_logic; -- lock []
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sel : wishbone_byte_select_t;
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stb : std_logic; -- strobe [mandatory RULE 3.40]
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tga : wishbone_tag_address_t; -- address tag []
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tgc : wishbone_tag_cycle_t; -- cycle tag []
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we : std_logic; -- write enable []
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end record wishbone_master_out_t;
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subtype wishbone_slave_in_t is wishbone_master_out_t;
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type wishbone_slave_out_t is record
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-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
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dat : wishbone_data_t; -- read data []
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tgd : wishbone_tag_data_t; -- read data tag []
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-- 2.2.4 SLAVE Signals
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ack : std_logic; -- acknowledge [mandatory RULE 3.40]
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err : std_logic; -- error [optional PERMISSION 3.20]
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rty : std_logic; -- retry [optional PERMISSION 3.25]
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--stall : std_logic;
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int : std_logic; -- interrupt [non WB signal]
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end record wishbone_slave_out_t;
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subtype wishbone_master_in_t is wishbone_slave_out_t;
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-- subtype wishbone_device_descriptor_t is std_logic_vector(255 downto 0);
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-- type wishbone_byte_select_array_t is array(natural range <>) of wishbone_byte_select_t;
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-- type wishbone_data_array_t is array(natural range <>) of wishbone_data_t;
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type wishbone_address_array_t is array(natural range <>) of wishbone_address_t;
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type wishbone_master_out_array_t is array (natural range <>) of wishbone_master_out_t;
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type wishbone_slave_in_array_t is array (natural range <>) of wishbone_slave_in_t;
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-- subtype wishbone_slave_in_array_t is wishbone_master_out_array_t;
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type wishbone_slave_out_array_t is array (natural range <>) of wishbone_slave_out_t;
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--type wishbone_master_in_array_t is array (natural range <>) of wishbone_master_in_t;
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subtype wishbone_master_in_array_t is wishbone_slave_out_array_t;
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constant wb_master_out_idle_c : wishbone_master_out_t := (
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clk => '0',
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dat => wishbone_data_of_unused_address_c,
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rst => '0',
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tgd => (others=>'0'),
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adr => (others=>'U'),
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cyc => '0',
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lock => '0',
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sel => (others=>'0'),
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stb => '0',
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tga => (others=>'0'),
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tgc => (others=>'0'),
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we => '0'
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);
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-- constant cc_dummy_address : std_logic_vector(wishbone_address_width_c-1 downto 0) :=(others => 'X');
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-- constant cc_dummy_data : std_logic_vector(wishbone_address_width_c-1 downto 0) := (others => 'X');
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-- constant cc_dummy_sel : std_logic_vector(wishbone_data_width_c/8-1 downto 0) := (others => 'X');
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-- constant cc_dummy_slave_in : wishbone_slave_in_t :=('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
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-- constant cc_dummy_master_out : wishbone_master_out_t := cc_dummy_slave_in;
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-- -- Dangerous! Will stall a bus.
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-- constant cc_dummy_slave_out : wishbone_slave_out_t :=('X', 'X', 'X', 'X', 'X', cc_dummy_data);
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-- constant cc_dummy_master_in : wishbone_master_in_t := cc_dummy_slave_out;
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-- constant cc_dummy_address_array : wishbone_address_array_t(0 downto 0) := (0 => cc_dummy_address);
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end wishbone_pkg;
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-- package body ------------------------------------------------------
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package body wishbone_pkg is
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end wishbone_pkg;
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----------------------------------------------------------------------
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---- end of file ----
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----------------------------------------------------------------------
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