URL https://opencores.org/ocsvn/vhld_tb/vhld_tb/trunk

Subversion Repositories vhld_tb

[/] [vhld_tb/] [trunk/] [examples/] [example1/] [vhdl/] [example_dut_ttb_str.vhd] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log


--  structure file generated by ttb_gen
architecture struct of example_dut_ttb is
 
component example_dut
  port (
        ex_reset_n : in      std_logic;
        ex_clk_in  : in      std_logic;
        ex_data1   : out     std_logic_vector(31 downto 0);
        ex_data2   : out     std_logic_vector(31 downto 0);
        stm_add    : in      std_logic_vector(31 downto 0);
        stm_dat    : inout   std_logic_vector(31 downto 0);
        stm_rwn    : in      std_logic;
        stm_req_n  : in      std_logic;
        stm_ack_n  : out     std_logic
       );
end component;
 
component example_dut_tb
  generic (
           stimulus_file: in string
          );
  port (
        ex_reset_n : buffer  std_logic;
        ex_clk_in  : buffer  std_logic;
        ex_data1   : in      std_logic_vector(31 downto 0);
        ex_data2   : in      std_logic_vector(31 downto 0);
        stm_add    : buffer  std_logic_vector(31 downto 0);
        stm_dat    : inout   std_logic_vector(31 downto 0);
        stm_rwn    : buffer  std_logic;
        stm_req_n  : buffer  std_logic;
        stm_ack_n  : in      std_logic
       );
end component;
 
--for all: example_dut    use entity dut_lib.example_dut(str);
--for all: example_dut_tb    use entity work.example_dut_tb(bhv);
 
  signal temp_ex_reset_n : std_logic;
  signal temp_ex_clk_in  : std_logic;
  signal temp_ex_data1   : std_logic_vector(31 downto 0);
  signal temp_ex_data2   : std_logic_vector(31 downto 0);
  signal temp_stm_add    : std_logic_vector(31 downto 0);
  signal temp_stm_dat    : std_logic_vector(31 downto 0);
  signal temp_stm_rwn    : std_logic;
  signal temp_stm_req_n  : std_logic;
  signal temp_stm_ack_n  : std_logic;
 
begin
 
dut: example_dut
  port map(
           ex_reset_n =>  temp_ex_reset_n,
           ex_clk_in  =>  temp_ex_clk_in,
           ex_data1   =>  temp_ex_data1,
           ex_data2   =>  temp_ex_data2,
           stm_add    =>  temp_stm_add,
           stm_dat    =>  temp_stm_dat,
           stm_rwn    =>  temp_stm_rwn,
           stm_req_n  =>  temp_stm_req_n,
           stm_ack_n  =>  temp_stm_ack_n
          );
 
tb: example_dut_tb
  generic map(
               stimulus_file => stimulus_file
             )
  port map(
           ex_reset_n =>  temp_ex_reset_n,
           ex_clk_in  =>  temp_ex_clk_in,
           ex_data1   =>  temp_ex_data1,
           ex_data2   =>  temp_ex_data2,
           stm_add    =>  temp_stm_add,
           stm_dat    =>  temp_stm_dat,
           stm_rwn    =>  temp_stm_rwn,
           stm_req_n  =>  temp_stm_req_n,
           stm_ack_n  =>  temp_stm_ack_n
          );
 
end struct;

Line No.	Rev	Author	Line
1	5	sckoarn	`-- structure file generated by ttb_gen`
2			`architecture struct of example_dut_ttb is`
3
4			`component example_dut`
5			`port (`
6			`ex_reset_n : in std_logic;`
7			`ex_clk_in : in std_logic;`
8			`ex_data1 : out std_logic_vector(31 downto 0);`
9			`ex_data2 : out std_logic_vector(31 downto 0);`
10			`stm_add : in std_logic_vector(31 downto 0);`
11			`stm_dat : inout std_logic_vector(31 downto 0);`
12			`stm_rwn : in std_logic;`
13			`stm_req_n : in std_logic;`
14			`stm_ack_n : out std_logic`
15			`);`
16			`end component;`
17
18			`component example_dut_tb`
19			`generic (`
20			`stimulus_file: in string`
21			`);`
22			`port (`
23			`ex_reset_n : buffer std_logic;`
24			`ex_clk_in : buffer std_logic;`
25			`ex_data1 : in std_logic_vector(31 downto 0);`
26			`ex_data2 : in std_logic_vector(31 downto 0);`
27			`stm_add : buffer std_logic_vector(31 downto 0);`
28			`stm_dat : inout std_logic_vector(31 downto 0);`
29			`stm_rwn : buffer std_logic;`
30			`stm_req_n : buffer std_logic;`
31			`stm_ack_n : in std_logic`
32			`);`
33			`end component;`
34
35			`--for all: example_dut use entity dut_lib.example_dut(str);`
36			`--for all: example_dut_tb use entity work.example_dut_tb(bhv);`
37
38			`signal temp_ex_reset_n : std_logic;`
39			`signal temp_ex_clk_in : std_logic;`
40			`signal temp_ex_data1 : std_logic_vector(31 downto 0);`
41			`signal temp_ex_data2 : std_logic_vector(31 downto 0);`
42			`signal temp_stm_add : std_logic_vector(31 downto 0);`
43			`signal temp_stm_dat : std_logic_vector(31 downto 0);`
44			`signal temp_stm_rwn : std_logic;`
45			`signal temp_stm_req_n : std_logic;`
46			`signal temp_stm_ack_n : std_logic;`
47
48			`begin`
49
50			`dut: example_dut`
51			`port map(`
52			`ex_reset_n => temp_ex_reset_n,`
53			`ex_clk_in => temp_ex_clk_in,`
54			`ex_data1 => temp_ex_data1,`
55			`ex_data2 => temp_ex_data2,`
56			`stm_add => temp_stm_add,`
57			`stm_dat => temp_stm_dat,`
58			`stm_rwn => temp_stm_rwn,`
59			`stm_req_n => temp_stm_req_n,`
60			`stm_ack_n => temp_stm_ack_n`
61			`);`
62
63			`tb: example_dut_tb`
64			`generic map(`
65			`stimulus_file => stimulus_file`
66			`)`
67			`port map(`
68			`ex_reset_n => temp_ex_reset_n,`
69			`ex_clk_in => temp_ex_clk_in,`
70			`ex_data1 => temp_ex_data1,`
71			`ex_data2 => temp_ex_data2,`
72			`stm_add => temp_stm_add,`
73			`stm_dat => temp_stm_dat,`
74			`stm_rwn => temp_stm_rwn,`
75			`stm_req_n => temp_stm_req_n,`
76			`stm_ack_n => temp_stm_ack_n`
77			`);`
78
79			`end struct;`

Browse

Tools

Subversion Repositories vhld_tb

[/] [vhld_tb/] [trunk/] [examples/] [example1/] [vhdl/] [example_dut_ttb_str.vhd] - Blame information for rev 5