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[/] [video_systems/] [trunk/] [common/] [entropy_coding/] [rtl/] [verilog/] [huffman_dec.v] - Blame information for rev 9

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1 9 rherveille
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  JPEG Entropy Coding, Huffman Decoding                      ////
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////                                                             ////
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////  Decomposes incomming datastream into packets for the       ////
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////  Huffman tables.                                            ////
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////  See accompanying testbench how to use this code.           ////
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////                                                             ////
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////  Author: Richard Herveille                                  ////
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////          richard@asics.ws                                   ////
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////          www.asics.ws                                       ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2001 Richard Herveille                        ////
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////                    richard@asics.ws                         ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: huffman_dec.v,v 1.1 2002-10-29 20:07:53 rherveille Exp $
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//
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//  $Date: 2002-10-29 20:07:53 $
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//  $Revision: 1.1 $
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//  $Author: rherveille $
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//  $Locker:  $
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//  $State: Exp $
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//
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`include "timescale.v"
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module huffman_dec(clk, rst, tablesel, di, die, do, doe, busy);
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  input         clk;      // clock
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  input         rst;      // asynchronous active low reset
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  input  [ 1:0] tablesel; // huffman table select
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  input  [ 7:0] di;       // data input
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  input         die;      // data-in enable
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  output [ 7:0] do;       // category or Runlenght/Size codepair
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  output        doe;      // data-out enable
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  output        busy;     // busy. Do not assert die while busy asserted
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  reg [7:0] do;
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  reg       doe, busy;
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  wire [ 7:0] hdec_dc_lum, hdec_dc_chr;
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  wire [11:0] hdec_ac_lum, hdec_ac_chr;
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  reg  [ 4:0] codelen;
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  reg  [15:0] code;
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  reg [ 1:0] state;
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  reg [22:0] sreg;
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  reg [ 4:0] cnt;
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  `include "huffman_tables.v"
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  //
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  // hookup huffman tables
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  //
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  assign hdec_dc_lum = jpeg_dc_luminance_huffman_dec(code[15:7]);
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  assign hdec_dc_chr = jpeg_dc_chrominance_huffman_dec(code[15:5]);
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  assign hdec_ac_lum = jpeg_ac_luminance_huffman_dec(code);
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  assign hdec_ac_chr = jpeg_ac_chrominance_huffman_dec(code);
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  //
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  // split table data into category Run/Size and codelength
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  //
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  always @(posedge clk)
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    case (tablesel) // synopsys full_case parallel_case
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      2'b00: // DC Luminance
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        begin
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            codelen <= #1 hdec_dc_lum[ 7: 4] +4'h1;
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            do      <= #1 {4'h0, hdec_dc_lum[ 3: 0]};
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        end
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      2'b01: // DC Chrominance
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        begin
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            codelen <= #1 hdec_dc_chr[ 7: 4] +4'h1;
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            do      <= #1 {4'h0, hdec_dc_chr[ 3: 0]};
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        end
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      2'b10: // AC Luminance
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        begin
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            codelen <= #1 hdec_ac_lum[11:8] +4'h1;
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            do      <= #1 hdec_ac_lum[ 7:0];
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        end
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      2'b11: // AC Chrominance
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        begin
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            codelen <= #1 hdec_ac_chr[11:8] +4'h1;
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            do      <= #1 hdec_ac_chr[ 7:0];
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        end
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    endcase
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  //
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  // Hookup din statemachine
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  //
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  always @(posedge clk or negedge rst)
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    if(~rst)
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      begin
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          state <= #1 2'b00;
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          sreg  <= #1 24'h0;
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          cnt   <= #1 5'h0;
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          busy  <= #1 1'b0;
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      end
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    else
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      begin
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          doe <= #1 1'b0;
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          case(state)
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            2'b00:
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                if(die)
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                  begin
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                      if( (cnt + 5'h8) > 15 ) // guaranteed valid code in sreg
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                        begin
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                            state <= #1 2'b01;
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                            busy  <= #1 1'b1;
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                        end
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                        sreg <= #1 ((sreg << 8) | di);
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                        cnt  <= #1 (cnt + 5'h8);
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                  end
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            2'b01:
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                begin
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                    state <= #1 2'b11; // wait for codelen (data from table)
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                    doe   <= #1 1'b1;
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                end
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            2'b11:
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                begin
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                    if( (cnt - codelen) > 15 ) // still valid codes in sreg
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                      state <= #1 2'b01;
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                    else
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                      begin
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                          state <= #1 2'b00;
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                          busy  <= #1 1'b0;
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                      end
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                    cnt  <= #1 (cnt - codelen);
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                end
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          endcase
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      end
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  always @(posedge clk)
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    if(die)
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      code <= #1 ((sreg << 8) | di) >> ((cnt + 5'h8) -5'h10);
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    else
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      code <= #1 sreg >> ((cnt - codelen) -5'h10);
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endmodule

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