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[/] [video_systems/] [trunk/] [common/] [entropy_coding/] [rtl/] [verilog/] [huffman_enc.v] - Blame information for rev 25

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1 9 rherveille
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  JPEG Entropy Coding, Huffman Encoding                      ////
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////                                                             ////
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////  Creates 8bit output stream from huffman codes.             ////
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////  See accompanying testbench how to use this code.           ////
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////                                                             ////
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////  Author: Richard Herveille                                  ////
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////          richard@asics.ws                                   ////
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////          www.asics.ws                                       ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2001 Richard Herveille                        ////
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////                    richard@asics.ws                         ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: huffman_enc.v,v 1.2 2002-10-31 12:50:40 rherveille Exp $
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//
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//  $Date: 2002-10-31 12:50:40 $
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//  $Revision: 1.2 $
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//  $Author: rherveille $
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//  $Locker:  $
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//  $State: Exp $
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module huffman_enc(clk, rst, tablesel, di, die, do, doe, busy);
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  input        clk;      // clock
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  input        rst;      // asynchronous active low reset
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  input  [1:0] tablesel; // huffman table select (0-3)
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  input  [7:0] di;       // data-in
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  input        die;      // data-in enable
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  output [7:0] do;       // data out
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  output       doe;      // data-out enable
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  output       busy;     // busy. Do not assert die while busy asserted
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  reg [7:0] do;
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  reg       doe;
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  wire [12:0] henc_dc_lum;
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  wire [14:0] henc_dc_chr;
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  wire [19:0] henc_ac_lum, henc_ac_chr;
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  reg  [ 4:0] codelen;
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  reg  [15:0] code;
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  reg         ddie;
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  reg         state;
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  reg  [22:0] sreg;
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  reg  [ 4:0] cnt;
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  // include default tables
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  `include "huffman_tables.v"
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  //
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  // hookup huffman tables
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  //
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  assign henc_dc_lum = jpeg_dc_luminance_huffman_enc( di[3:0] );
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  assign henc_dc_chr = jpeg_dc_chrominance_huffman_enc( di[3:0] );
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  assign henc_ac_lum = jpeg_ac_luminance_huffman_enc( di[7:4], di[3:0] );
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  assign henc_ac_chr = jpeg_ac_chrominance_huffman_enc( di[7:4], di[3:0] );
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  //
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  // split table-data into codeword and codeword-length
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  //
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  always @(posedge clk)
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    case (tablesel) // synopsys full_case parallel_case
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      2'b00: // DC Luminance
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        begin
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            codelen <= #1 henc_dc_lum[12: 9] +4'h1;
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            code    <= #1 henc_dc_lum[ 8: 0];
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        end
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      2'b01: // DC Chrominance
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        begin
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            codelen <= #1 henc_dc_chr[14:11] +4'h1;
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            code    <= #1 henc_dc_chr[10: 0];
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        end
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      2'b10: // AC Luminance
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        begin
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            codelen <= #1 henc_ac_lum[19:16] +4'h1;
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            code    <= #1 henc_ac_lum[15: 0];
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        end
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      2'b11: // AC Chrominance
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        begin
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            codelen <= #1 henc_ac_chr[19:16] +4'h1;
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            code    <= #1 henc_ac_chr[15: 0];
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        end
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    endcase
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  //
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  // wait for encoder table(s)
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  //
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  always @(posedge clk)
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    ddie <= #1 die;
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  //
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  // data out statemachine
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  //
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  always @(posedge clk or negedge rst)
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    if(~rst)
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      begin
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          state <= #1 1'b0;
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          cnt   <= #1 5'h0;
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      end
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    else
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      case (state)
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        1'b0:
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         if(ddie)
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           begin
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               if( (cnt + codelen) > 7 )
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                 state <= #1 1'b1;
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               cnt <= #1 (cnt + codelen);
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           end
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        1'b1:
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         begin
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             if (ddie)
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             begin
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                 cnt <= #1 (cnt + codelen) - 5'h8;
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                 if( (cnt + codelen) - 5'h8 < 8)
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                   state <= #1 1'b0;
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             end
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             else
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             begin
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                if( (cnt -5'h8) < 8)
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                  state <= #1 1'b0;
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                cnt <= #1 (cnt -5'h8);
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             end
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         end
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      endcase
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  assign busy = state;
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  always @(posedge clk)
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    if(ddie)
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      sreg <= #1 (sreg << codelen) | code;
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  always @(posedge clk)
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    doe <= #1 state;
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  always @(posedge clk)
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    do <= #1 sreg >> (cnt -5'h8);
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endmodule

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