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[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [ACS.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 sandunrath
module ACS
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(
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   path_0_valid,
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   path_1_valid,
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   path_0_bmc,
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   path_1_bmc,
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   path_0_pmc,
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   path_1_pmc,
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   selection,
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   valid_o,
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   path_cost
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);
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   input       path_0_valid;
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   input [1:0] path_0_bmc;
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   input [7:0] path_0_pmc;
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   input       path_1_valid;
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   input [1:0] path_1_bmc;
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   input [7:0] path_1_pmc;
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   output reg        selection;
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   output reg        valid_o;
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   output      [7:0] path_cost;
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   wire  [7:0] path_cost_0;
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   wire  [7:0] path_cost_1;
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   assign path_cost_0  =  path_0_bmc + path_0_pmc;
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   assign path_cost_1  =  path_1_bmc + path_1_pmc;
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   assign path_cost      =  (valid_o?(selection?path_cost_1:path_cost_0):7'd0);
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   always @ (*)
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   begin
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      valid_o = 1'b1;
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      case({path_0_valid,path_1_valid})
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         2'b00:
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         begin
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            selection = 1'b0;
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            valid_o   = 1'b0;
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         end
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         2'b01:   selection = 1'b1;
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         2'b10:   selection = 1'b0;
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         2'b11:   selection = (path_cost_0 > path_cost_1)?1'b1:1'b0;
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       endcase
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   end
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endmodule

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