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[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [backup/] [decoder_20120201_1.v] - Blame information for rev 2

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module decoder
(
   clk,
   rst,
   d_in,
   d_out
);
 
   input             clk;
   input             rst;
   input [1:0]       d_in;
   output            d_out;
 
   reg               decoder_o_reg;
 
 
//bmc module signals
   wire  [1:0]       bmc000_path_0_bmc;
   wire  [1:0]       bmc001_path_0_bmc;
   wire  [1:0]       bmc010_path_0_bmc;
   wire  [1:0]       bmc011_path_0_bmc;
   wire  [1:0]       bmc100_path_0_bmc;
   wire  [1:0]       bmc101_path_0_bmc;
   wire  [1:0]       bmc110_path_0_bmc;
   wire  [1:0]       bmc111_path_0_bmc;
 
   wire  [1:0]       bmc000_path_1_bmc;
   wire  [1:0]       bmc001_path_1_bmc;
   wire  [1:0]       bmc010_path_1_bmc;
   wire  [1:0]       bmc011_path_1_bmc;
   wire  [1:0]       bmc100_path_1_bmc;
   wire  [1:0]       bmc101_path_1_bmc;
   wire  [1:0]       bmc110_path_1_bmc;
   wire  [1:0]       bmc111_path_1_bmc;
 
//ACS modules signals
   reg   [7:0]       validity;
   reg   [7:0]       selection;
   reg   [7:0]       path_cost   [7:0];
   wire  [7:0]       validity_nets;
   wire  [7:0]       selection_nets;
 
   wire              ACS000_selection;
   wire              ACS001_selection;
   wire              ACS010_selection;
   wire              ACS011_selection;
   wire              ACS100_selection;
   wire              ACS101_selection;
   wire              ACS110_selection;
   wire              ACS111_selection;
 
   wire              ACS000_valid_o;
   wire              ACS001_valid_o;
   wire              ACS010_valid_o;
   wire              ACS011_valid_o;
   wire              ACS100_valid_o;
   wire              ACS101_valid_o;
   wire              ACS110_valid_o;
   wire              ACS111_valid_o;
 
   wire  [7:0]       ACS000_path_cost;
   wire  [7:0]       ACS001_path_cost;
   wire  [7:0]       ACS010_path_cost;
   wire  [7:0]       ACS011_path_cost;
   wire  [7:0]       ACS100_path_cost;
   wire  [7:0]       ACS101_path_cost;
   wire  [7:0]       ACS110_path_cost;
   wire  [7:0]       ACS111_path_cost;
 
//Trelis memory write operation
   reg   [1:0]       mem_bank;
   reg   [1:0]       mem_bank_buf;
   reg   [1:0]       mem_bank_buf_buf;
   reg   [1:0]       mem_bank_buf_buf_buf;
   reg   [1:0]       mem_bank_buf_buf_buf_buf;
   reg   [1:0]       mem_bank_buf_buf_buf_buf_buf;
   reg   [9:0]       wr_mem_counter;
   reg   [9:0]       rd_mem_counter;
 
   reg   [9:0]       addr_mem_A;
   reg   [9:0]       addr_mem_B;
   reg   [9:0]       addr_mem_C;
   reg   [9:0]       addr_mem_D;
 
   reg               wr_mem_A;
   reg               wr_mem_B;
   reg               wr_mem_C;
   reg               wr_mem_D;
 
   reg   [7:0]       d_in_mem_A;
   reg   [7:0]       d_in_mem_B;
   reg   [7:0]       d_in_mem_C;
   reg   [7:0]       d_in_mem_D;
 
   wire  [7:0]       d_o_mem_A;
   wire  [7:0]       d_o_mem_B;
   wire  [7:0]       d_o_mem_C;
   wire  [7:0]       d_o_mem_D;
 
//Trace back module signals
   reg               selection_tbu_0;
   reg               selection_tbu_1;
 
   reg   [7:0]       d_in_0_tbu_0;
   reg   [7:0]       d_in_1_tbu_0;
   reg   [7:0]       d_in_0_tbu_1;
   reg   [7:0]       d_in_1_tbu_1;
 
   wire              d_o_tbu_0;
   wire              d_o_tbu_1;
 
//Display memory operations 
   wire              wr_disp_mem_0;
   wire              wr_disp_mem_1;
 
   wire              d_in_disp_mem_0;
   wire              d_in_disp_mem_1;
 
   reg   [9:0]       wr_mem_counter_disp;
   reg   [9:0]       rd_mem_counter_disp;
 
   reg   [9:0]       addr_disp_mem_0;
   reg   [9:0]       addr_disp_mem_1;
 
 
   assign   d_out =  decoder_o_reg;
 
 
//Branch matrc calculation modules
 
   bmc000   bmc000_inst(d_in,bmc000_path_0_bmc,bmc000_path_1_bmc);
   bmc001   bmc001_inst(d_in,bmc001_path_0_bmc,bmc001_path_1_bmc);
   bmc010   bmc010_inst(d_in,bmc010_path_0_bmc,bmc010_path_1_bmc);
   bmc011   bmc011_inst(d_in,bmc011_path_0_bmc,bmc011_path_1_bmc);
   bmc100   bmc100_inst(d_in,bmc100_path_0_bmc,bmc100_path_1_bmc);
   bmc101   bmc101_inst(d_in,bmc101_path_0_bmc,bmc101_path_1_bmc);
   bmc110   bmc110_inst(d_in,bmc110_path_0_bmc,bmc110_path_1_bmc);
   bmc111   bmc111_inst(d_in,bmc111_path_0_bmc,bmc111_path_1_bmc);
 
 
//Add Compare Select Modules
 
   ACS      ACS000(validity[0],validity[1],bmc000_path_0_bmc,bmc000_path_1_bmc,path_cost[0],path_cost[1],ACS000_selection,ACS000_valid_o,ACS000_path_cost);
   ACS      ACS001(validity[3],validity[2],bmc001_path_0_bmc,bmc001_path_1_bmc,path_cost[3],path_cost[2],ACS001_selection,ACS001_valid_o,ACS001_path_cost);
   ACS      ACS010(validity[4],validity[5],bmc010_path_0_bmc,bmc010_path_1_bmc,path_cost[4],path_cost[5],ACS010_selection,ACS010_valid_o,ACS010_path_cost);
   ACS      ACS011(validity[7],validity[6],bmc011_path_0_bmc,bmc011_path_1_bmc,path_cost[7],path_cost[6],ACS011_selection,ACS011_valid_o,ACS011_path_cost);
   ACS      ACS100(validity[1],validity[0],bmc100_path_0_bmc,bmc100_path_1_bmc,path_cost[1],path_cost[0],ACS100_selection,ACS100_valid_o,ACS100_path_cost);
   ACS      ACS101(validity[2],validity[3],bmc101_path_0_bmc,bmc101_path_1_bmc,path_cost[2],path_cost[3],ACS101_selection,ACS101_valid_o,ACS101_path_cost);
   ACS      ACS110(validity[5],validity[4],bmc110_path_0_bmc,bmc110_path_1_bmc,path_cost[5],path_cost[4],ACS110_selection,ACS110_valid_o,ACS110_path_cost);
   ACS      ACS111(validity[6],validity[7],bmc111_path_0_bmc,bmc111_path_1_bmc,path_cost[6],path_cost[7],ACS111_selection,ACS111_valid_o,ACS111_path_cost);
 
 
   assign selection_nets  =  {ACS111_selection,ACS110_selection,ACS101_selection,ACS100_selection,
                              ACS011_selection,ACS010_selection,ACS001_selection,ACS000_selection};
   assign validity_nets    =  {ACS111_valid_o,ACS110_valid_o,ACS101_valid_o,ACS100_valid_o,
                              ACS011_valid_o,ACS010_valid_o,ACS001_valid_o,ACS000_valid_o};
 
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
      begin
         validity          <= 8'b00000001;
         selection         <= 8'b00000001;
 
         path_cost[0]      <= 8'd0;
         path_cost[1]      <= 8'd0;
         path_cost[2]      <= 8'd0;
         path_cost[3]      <= 8'd0;
         path_cost[4]      <= 8'd0;
         path_cost[5]      <= 8'd0;
         path_cost[6]      <= 8'd0;
         path_cost[7]      <= 8'd0;
 
      end
      else begin
         validity          <= validity_nets;
         selection         <= selection_nets;
 
         path_cost[0]      <= ACS000_path_cost;
         path_cost[1]      <= ACS001_path_cost;
         path_cost[2]      <= ACS010_path_cost;
         path_cost[3]      <= ACS011_path_cost;
         path_cost[4]      <= ACS100_path_cost;
         path_cost[5]      <= ACS101_path_cost;
         path_cost[6]      <= ACS110_path_cost;
         path_cost[7]      <= ACS111_path_cost;
 
      end
   end
 
 
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
         wr_mem_counter <= 10'd0;
      else
         wr_mem_counter <= wr_mem_counter + 10'd1;
   end
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
         rd_mem_counter <= 10'b1111111111;
      else
         rd_mem_counter <= rd_mem_counter - 10'd1;
   end
 
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
         mem_bank <= 2'b00;
      else begin
         if(wr_mem_counter==10'b1111111111)
               mem_bank <= mem_bank + 2'b01;
      end
   end
 
 
   always @ (posedge clk)
   begin
      d_in_mem_A  <= selection;
      d_in_mem_B  <= selection;
      d_in_mem_C  <= selection;
      d_in_mem_D  <= selection;
 
   end
 
 
   always @ (posedge clk)
   begin
      case(mem_bank)
         2'b00:
         begin
            addr_mem_A        <= wr_mem_counter;
            addr_mem_B        <= rd_mem_counter;
            addr_mem_C        <= 10'd0;
            addr_mem_D        <= rd_mem_counter;
 
            wr_mem_A          <= 1'b1;
            wr_mem_B          <= 1'b0;
            wr_mem_C          <= 1'b0;
            wr_mem_D          <= 1'b0;
         end
         2'b01:
         begin
            addr_mem_A        <= rd_mem_counter;
            addr_mem_B        <= wr_mem_counter;
            addr_mem_C        <= rd_mem_counter;
            addr_mem_D        <= 10'd0;
 
            wr_mem_A          <= 1'b0;
            wr_mem_B          <= 1'b1;
            wr_mem_C          <= 1'b0;
            wr_mem_D          <= 1'b0;
 
         end
         2'b10:
         begin
            addr_mem_A        <= 10'd0;
            addr_mem_B        <= rd_mem_counter;
            addr_mem_C        <= wr_mem_counter;
            addr_mem_D        <= rd_mem_counter;
 
            wr_mem_A          <= 1'b0;
            wr_mem_B          <= 1'b0;
            wr_mem_C          <= 1'b1;
            wr_mem_D          <= 1'b0;
         end
         2'b11:
         begin
            addr_mem_A        <= rd_mem_counter;
            addr_mem_B        <= 10'd0;
            addr_mem_C        <= rd_mem_counter;
            addr_mem_D        <= wr_mem_counter;
 
            wr_mem_A          <= 1'b0;
            wr_mem_B          <= 1'b0;
            wr_mem_C          <= 1'b0;
            wr_mem_D          <= 1'b1;
         end
      endcase
  end
 
//Trelis memory module instantiation
 
   mem   trelis_mem_A
   (
      .clk(clk),
      .wr(wr_mem_A),
      .addr(addr_mem_A),
      .d_i(d_in_mem_A),
      .d_o(d_o_mem_A)
   );
 
  mem   trelis_mem_B
   (
      .clk(clk),
      .wr(wr_mem_B),
      .addr(addr_mem_B),
      .d_i(d_in_mem_B),
      .d_o(d_o_mem_B)
   );
 
  mem   trelis_mem_C
   (
      .clk(clk),
      .wr(wr_mem_C),
      .addr(addr_mem_C),
      .d_i(d_in_mem_C),
      .d_o(d_o_mem_C)
   );
 
  mem   trelis_mem_D
   (
      .clk(clk),
      .wr(wr_mem_D),
      .addr(addr_mem_D),
      .d_i(d_in_mem_D),
      .d_o(d_o_mem_D)
   );
 
//Trace back module operation
 
   always @(posedge clk)
      mem_bank_buf   <= mem_bank;
 
   always @(posedge clk)
      mem_bank_buf_buf   <= mem_bank_buf;
 
   always @ (posedge clk)
   begin
      case(mem_bank_buf_buf)
         2'b00:
         begin
            d_in_0_tbu_0   <= d_o_mem_D;
            d_in_1_tbu_0   <= d_o_mem_C;
 
            d_in_0_tbu_1   <= d_o_mem_C;
            d_in_1_tbu_1   <= d_o_mem_B;
 
            selection_tbu_0<= 1'b0;
            selection_tbu_1<= 1'b1;
 
         end
         2'b01:
         begin
            d_in_0_tbu_0   <= d_o_mem_D;
            d_in_1_tbu_0   <= d_o_mem_C;
 
            d_in_0_tbu_1   <= d_o_mem_A;
            d_in_1_tbu_1   <= d_o_mem_D;
 
            selection_tbu_0<= 1'b1;
            selection_tbu_1<= 1'b0;
         end
         2'b10:
         begin
            d_in_0_tbu_0   <= d_o_mem_B;
            d_in_1_tbu_0   <= d_o_mem_A;
 
            d_in_0_tbu_1   <= d_o_mem_A;
            d_in_1_tbu_1   <= d_o_mem_D;
 
            selection_tbu_0<= 1'b0;
            selection_tbu_1<= 1'b1;
         end
         2'b11:
         begin
            d_in_0_tbu_0   <= d_o_mem_B;
            d_in_1_tbu_0   <= d_o_mem_A;
 
            d_in_0_tbu_1   <= d_o_mem_C;
            d_in_1_tbu_1   <= d_o_mem_B;
 
            selection_tbu_0<= 1'b1;
            selection_tbu_1<= 1'b0;
         end
      endcase
   end
 
//Trace-Back modules instantiation
 
   tbu tbu_0
   (
      .clk(clk),
      .rst(rst),
      .selection(selection_tbu_0),
      .d_in_0(d_in_0_tbu_0),
      .d_in_1(d_in_1_tbu_0),
      .d_o(d_o_tbu_0),
      .wr_en(wr_disp_mem_0)
   );
 
   tbu tbu_1
   (
      .clk(clk),
      .rst(rst),
      .selection(selection_tbu_1),
      .d_in_0(d_in_0_tbu_1),
      .d_in_1(d_in_1_tbu_1),
      .d_o(d_o_tbu_1),
      .wr_en(wr_disp_mem_1)
   );
 
//Display Memory modules Instantioation
 
   assign   d_in_disp_mem_0   =  d_o_tbu_0;
   assign   d_in_disp_mem_1   =  d_o_tbu_1;
 
 
  mem_disp   disp_mem_0
  (
      .clk(clk),
      .wr(wr_disp_mem_0),
      .addr(addr_disp_mem_0),
      .d_i(d_in_disp_mem_0),
      .d_o(d_o_disp_mem_0)
   );
 
  mem_disp   disp_mem_1
  (
      .clk(clk),
      .wr(wr_disp_mem_1),
      .addr(addr_disp_mem_1),
      .d_i(d_in_disp_mem_1),
      .d_o(d_o_disp_mem_1)
   );
 
// Display memory module operation
   always @ (posedge clk)
      mem_bank_buf_buf_buf <= mem_bank_buf_buf;
 
   always @ (posedge clk)
   begin
      if(rst==1'b0)
         wr_mem_counter_disp  <= 10'b1111111100;
      else
         wr_mem_counter_disp  <= wr_mem_counter_disp + 10'd1;
   end
 
   always @ (posedge clk)
   begin
      if(rst==1'b0)
         rd_mem_counter_disp  <= 10'b0000000011;
      else
         rd_mem_counter_disp  <= rd_mem_counter_disp - 10'd1;
   end
 
 
   always @ (posedge clk)
   begin
      case(mem_bank_buf_buf_buf)
         2'b00:
         begin
            addr_disp_mem_0   <= rd_mem_counter_disp;
            addr_disp_mem_1   <= wr_mem_counter_disp;
         end
         2'b01:
         begin
            addr_disp_mem_0   <= wr_mem_counter_disp;
            addr_disp_mem_1   <= rd_mem_counter_disp;
            end
         2'b10:
         begin
            addr_disp_mem_0   <= rd_mem_counter_disp;
            addr_disp_mem_1   <= wr_mem_counter_disp;
         end
         2'b11:
         begin
            addr_disp_mem_0   <= wr_mem_counter_disp;
            addr_disp_mem_1   <= rd_mem_counter_disp;
         end
      endcase
   end
 
   always @ (posedge clk)
      mem_bank_buf_buf_buf_buf   <= mem_bank_buf_buf_buf;
 
   always @ (posedge clk)
      mem_bank_buf_buf_buf_buf_buf <= mem_bank_buf_buf_buf_buf;
 
 
 
   always @ (posedge clk)
   begin
      case(mem_bank_buf_buf_buf_buf_buf)
         2'b00:
         begin
            decoder_o_reg  <= d_o_disp_mem_0;
         end
         2'b01:
         begin
            decoder_o_reg  <= d_o_disp_mem_1;
         end
         2'b10:
         begin
            decoder_o_reg  <= d_o_disp_mem_1;
         end
         2'b11:
         begin
            decoder_o_reg  <= d_o_disp_mem_0;
         end
      endcase
   end
 
 
endmodule

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Subversion Repositories viterb_encoder_and_decoder

[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [backup/] [decoder_20120201_1.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sandunrath	`module decoder`
2			`(`
3			`clk,`
4			`rst,`
5			`d_in,`
6			`d_out`
7			`);`
8
9			`input clk;`
10			`input rst;`
11			`input [1:0] d_in;`
12			`output d_out;`
13
14			`reg decoder_o_reg;`
15
16
17			`//bmc module signals`
18			`wire [1:0] bmc000_path_0_bmc;`
19			`wire [1:0] bmc001_path_0_bmc;`
20			`wire [1:0] bmc010_path_0_bmc;`
21			`wire [1:0] bmc011_path_0_bmc;`
22			`wire [1:0] bmc100_path_0_bmc;`
23			`wire [1:0] bmc101_path_0_bmc;`
24			`wire [1:0] bmc110_path_0_bmc;`
25			`wire [1:0] bmc111_path_0_bmc;`
26
27			`wire [1:0] bmc000_path_1_bmc;`
28			`wire [1:0] bmc001_path_1_bmc;`
29			`wire [1:0] bmc010_path_1_bmc;`
30			`wire [1:0] bmc011_path_1_bmc;`
31			`wire [1:0] bmc100_path_1_bmc;`
32			`wire [1:0] bmc101_path_1_bmc;`
33			`wire [1:0] bmc110_path_1_bmc;`
34			`wire [1:0] bmc111_path_1_bmc;`
35
36			`//ACS modules signals`
37			`reg [7:0] validity;`
38			`reg [7:0] selection;`
39			`reg [7:0] path_cost [7:0];`
40			`wire [7:0] validity_nets;`
41			`wire [7:0] selection_nets;`
42
43			`wire ACS000_selection;`
44			`wire ACS001_selection;`
45			`wire ACS010_selection;`
46			`wire ACS011_selection;`
47			`wire ACS100_selection;`
48			`wire ACS101_selection;`
49			`wire ACS110_selection;`
50			`wire ACS111_selection;`
51
52			`wire ACS000_valid_o;`
53			`wire ACS001_valid_o;`
54			`wire ACS010_valid_o;`
55			`wire ACS011_valid_o;`
56			`wire ACS100_valid_o;`
57			`wire ACS101_valid_o;`
58			`wire ACS110_valid_o;`
59			`wire ACS111_valid_o;`
60
61			`wire [7:0] ACS000_path_cost;`
62			`wire [7:0] ACS001_path_cost;`
63			`wire [7:0] ACS010_path_cost;`
64			`wire [7:0] ACS011_path_cost;`
65			`wire [7:0] ACS100_path_cost;`
66			`wire [7:0] ACS101_path_cost;`
67			`wire [7:0] ACS110_path_cost;`
68			`wire [7:0] ACS111_path_cost;`
69
70			`//Trelis memory write operation`
71			`reg [1:0] mem_bank;`
72			`reg [1:0] mem_bank_buf;`
73			`reg [1:0] mem_bank_buf_buf;`
74			`reg [1:0] mem_bank_buf_buf_buf;`
75			`reg [1:0] mem_bank_buf_buf_buf_buf;`
76			`reg [1:0] mem_bank_buf_buf_buf_buf_buf;`
77			`reg [9:0] wr_mem_counter;`
78			`reg [9:0] rd_mem_counter;`
79
80			`reg [9:0] addr_mem_A;`
81			`reg [9:0] addr_mem_B;`
82			`reg [9:0] addr_mem_C;`
83			`reg [9:0] addr_mem_D;`
84
85			`reg wr_mem_A;`
86			`reg wr_mem_B;`
87			`reg wr_mem_C;`
88			`reg wr_mem_D;`
89
90			`reg [7:0] d_in_mem_A;`
91			`reg [7:0] d_in_mem_B;`
92			`reg [7:0] d_in_mem_C;`
93			`reg [7:0] d_in_mem_D;`
94
95			`wire [7:0] d_o_mem_A;`
96			`wire [7:0] d_o_mem_B;`
97			`wire [7:0] d_o_mem_C;`
98			`wire [7:0] d_o_mem_D;`
99
100			`//Trace back module signals`
101			`reg selection_tbu_0;`
102			`reg selection_tbu_1;`
103
104			`reg [7:0] d_in_0_tbu_0;`
105			`reg [7:0] d_in_1_tbu_0;`
106			`reg [7:0] d_in_0_tbu_1;`
107			`reg [7:0] d_in_1_tbu_1;`
108
109			`wire d_o_tbu_0;`
110			`wire d_o_tbu_1;`
111
112			`//Display memory operations`
113			`wire wr_disp_mem_0;`
114			`wire wr_disp_mem_1;`
115
116			`wire d_in_disp_mem_0;`
117			`wire d_in_disp_mem_1;`
118
119			`reg [9:0] wr_mem_counter_disp;`
120			`reg [9:0] rd_mem_counter_disp;`
121
122			`reg [9:0] addr_disp_mem_0;`
123			`reg [9:0] addr_disp_mem_1;`
124
125
126			`assign d_out = decoder_o_reg;`
127
128
129			`//Branch matrc calculation modules`
130
131			`bmc000 bmc000_inst(d_in,bmc000_path_0_bmc,bmc000_path_1_bmc);`
132			`bmc001 bmc001_inst(d_in,bmc001_path_0_bmc,bmc001_path_1_bmc);`
133			`bmc010 bmc010_inst(d_in,bmc010_path_0_bmc,bmc010_path_1_bmc);`
134			`bmc011 bmc011_inst(d_in,bmc011_path_0_bmc,bmc011_path_1_bmc);`
135			`bmc100 bmc100_inst(d_in,bmc100_path_0_bmc,bmc100_path_1_bmc);`
136			`bmc101 bmc101_inst(d_in,bmc101_path_0_bmc,bmc101_path_1_bmc);`
137			`bmc110 bmc110_inst(d_in,bmc110_path_0_bmc,bmc110_path_1_bmc);`
138			`bmc111 bmc111_inst(d_in,bmc111_path_0_bmc,bmc111_path_1_bmc);`
139
140
141			`//Add Compare Select Modules`
142
143			`ACS ACS000(validity[0],validity[1],bmc000_path_0_bmc,bmc000_path_1_bmc,path_cost[0],path_cost[1],ACS000_selection,ACS000_valid_o,ACS000_path_cost);`
144			`ACS ACS001(validity[3],validity[2],bmc001_path_0_bmc,bmc001_path_1_bmc,path_cost[3],path_cost[2],ACS001_selection,ACS001_valid_o,ACS001_path_cost);`
145			`ACS ACS010(validity[4],validity[5],bmc010_path_0_bmc,bmc010_path_1_bmc,path_cost[4],path_cost[5],ACS010_selection,ACS010_valid_o,ACS010_path_cost);`
146			`ACS ACS011(validity[7],validity[6],bmc011_path_0_bmc,bmc011_path_1_bmc,path_cost[7],path_cost[6],ACS011_selection,ACS011_valid_o,ACS011_path_cost);`
147			`ACS ACS100(validity[1],validity[0],bmc100_path_0_bmc,bmc100_path_1_bmc,path_cost[1],path_cost[0],ACS100_selection,ACS100_valid_o,ACS100_path_cost);`
148			`ACS ACS101(validity[2],validity[3],bmc101_path_0_bmc,bmc101_path_1_bmc,path_cost[2],path_cost[3],ACS101_selection,ACS101_valid_o,ACS101_path_cost);`
149			`ACS ACS110(validity[5],validity[4],bmc110_path_0_bmc,bmc110_path_1_bmc,path_cost[5],path_cost[4],ACS110_selection,ACS110_valid_o,ACS110_path_cost);`
150			`ACS ACS111(validity[6],validity[7],bmc111_path_0_bmc,bmc111_path_1_bmc,path_cost[6],path_cost[7],ACS111_selection,ACS111_valid_o,ACS111_path_cost);`
151
152
153			`assign selection_nets = {ACS111_selection,ACS110_selection,ACS101_selection,ACS100_selection,`
154			`ACS011_selection,ACS010_selection,ACS001_selection,ACS000_selection};`
155			`assign validity_nets = {ACS111_valid_o,ACS110_valid_o,ACS101_valid_o,ACS100_valid_o,`
156			`ACS011_valid_o,ACS010_valid_o,ACS001_valid_o,ACS000_valid_o};`
157
158
159			`always @ (posedge clk or negedge rst)`
160			`begin`
161			`if(rst==1'b0)`
162			`begin`
163			`validity <= 8'b00000001;`
164			`selection <= 8'b00000001;`
165
166			`path_cost[0] <= 8'd0;`
167			`path_cost[1] <= 8'd0;`
168			`path_cost[2] <= 8'd0;`
169			`path_cost[3] <= 8'd0;`
170			`path_cost[4] <= 8'd0;`
171			`path_cost[5] <= 8'd0;`
172			`path_cost[6] <= 8'd0;`
173			`path_cost[7] <= 8'd0;`
174
175			`end`
176			`else begin`
177			`validity <= validity_nets;`
178			`selection <= selection_nets;`
179
180			`path_cost[0] <= ACS000_path_cost;`
181			`path_cost[1] <= ACS001_path_cost;`
182			`path_cost[2] <= ACS010_path_cost;`
183			`path_cost[3] <= ACS011_path_cost;`
184			`path_cost[4] <= ACS100_path_cost;`
185			`path_cost[5] <= ACS101_path_cost;`
186			`path_cost[6] <= ACS110_path_cost;`
187			`path_cost[7] <= ACS111_path_cost;`
188
189			`end`
190			`end`
191
192
193
194			`always @ (posedge clk or negedge rst)`
195			`begin`
196			`if(rst==1'b0)`
197			`wr_mem_counter <= 10'd0;`
198			`else`
199			`wr_mem_counter <= wr_mem_counter + 10'd1;`
200			`end`
201
202			`always @ (posedge clk or negedge rst)`
203			`begin`
204			`if(rst==1'b0)`
205			`rd_mem_counter <= 10'b1111111111;`
206			`else`
207			`rd_mem_counter <= rd_mem_counter - 10'd1;`
208			`end`
209
210
211			`always @ (posedge clk or negedge rst)`
212			`begin`
213			`if(rst==1'b0)`
214			`mem_bank <= 2'b00;`
215			`else begin`
216			`if(wr_mem_counter==10'b1111111111)`
217			`mem_bank <= mem_bank + 2'b01;`
218			`end`
219			`end`
220
221
222			`always @ (posedge clk)`
223			`begin`
224			`d_in_mem_A <= selection;`
225			`d_in_mem_B <= selection;`
226			`d_in_mem_C <= selection;`
227			`d_in_mem_D <= selection;`
228
229			`end`
230
231
232			`always @ (posedge clk)`
233			`begin`
234			`case(mem_bank)`
235			`2'b00:`
236			`begin`
237			`addr_mem_A <= wr_mem_counter;`
238			`addr_mem_B <= rd_mem_counter;`
239			`addr_mem_C <= 10'd0;`
240			`addr_mem_D <= rd_mem_counter;`
241
242			`wr_mem_A <= 1'b1;`
243			`wr_mem_B <= 1'b0;`
244			`wr_mem_C <= 1'b0;`
245			`wr_mem_D <= 1'b0;`
246			`end`
247			`2'b01:`
248			`begin`
249			`addr_mem_A <= rd_mem_counter;`
250			`addr_mem_B <= wr_mem_counter;`
251			`addr_mem_C <= rd_mem_counter;`
252			`addr_mem_D <= 10'd0;`
253
254			`wr_mem_A <= 1'b0;`
255			`wr_mem_B <= 1'b1;`
256			`wr_mem_C <= 1'b0;`
257			`wr_mem_D <= 1'b0;`
258
259			`end`
260			`2'b10:`
261			`begin`
262			`addr_mem_A <= 10'd0;`
263			`addr_mem_B <= rd_mem_counter;`
264			`addr_mem_C <= wr_mem_counter;`
265			`addr_mem_D <= rd_mem_counter;`
266
267			`wr_mem_A <= 1'b0;`
268			`wr_mem_B <= 1'b0;`
269			`wr_mem_C <= 1'b1;`
270			`wr_mem_D <= 1'b0;`
271			`end`
272			`2'b11:`
273			`begin`
274			`addr_mem_A <= rd_mem_counter;`
275			`addr_mem_B <= 10'd0;`
276			`addr_mem_C <= rd_mem_counter;`
277			`addr_mem_D <= wr_mem_counter;`
278
279			`wr_mem_A <= 1'b0;`
280			`wr_mem_B <= 1'b0;`
281			`wr_mem_C <= 1'b0;`
282			`wr_mem_D <= 1'b1;`
283			`end`
284			`endcase`
285			`end`
286
287			`//Trelis memory module instantiation`
288
289			`mem trelis_mem_A`
290			`(`
291			`.clk(clk),`
292			`.wr(wr_mem_A),`
293			`.addr(addr_mem_A),`
294			`.d_i(d_in_mem_A),`
295			`.d_o(d_o_mem_A)`
296			`);`
297
298			`mem trelis_mem_B`
299			`(`
300			`.clk(clk),`
301			`.wr(wr_mem_B),`
302			`.addr(addr_mem_B),`
303			`.d_i(d_in_mem_B),`
304			`.d_o(d_o_mem_B)`
305			`);`
306
307			`mem trelis_mem_C`
308			`(`
309			`.clk(clk),`
310			`.wr(wr_mem_C),`
311			`.addr(addr_mem_C),`
312			`.d_i(d_in_mem_C),`
313			`.d_o(d_o_mem_C)`
314			`);`
315
316			`mem trelis_mem_D`
317			`(`
318			`.clk(clk),`
319			`.wr(wr_mem_D),`
320			`.addr(addr_mem_D),`
321			`.d_i(d_in_mem_D),`
322			`.d_o(d_o_mem_D)`
323			`);`
324
325			`//Trace back module operation`
326
327			`always @(posedge clk)`
328			`mem_bank_buf <= mem_bank;`
329
330			`always @(posedge clk)`
331			`mem_bank_buf_buf <= mem_bank_buf;`
332
333			`always @ (posedge clk)`
334			`begin`
335			`case(mem_bank_buf_buf)`
336			`2'b00:`
337			`begin`
338			`d_in_0_tbu_0 <= d_o_mem_D;`
339			`d_in_1_tbu_0 <= d_o_mem_C;`
340
341			`d_in_0_tbu_1 <= d_o_mem_C;`
342			`d_in_1_tbu_1 <= d_o_mem_B;`
343
344			`selection_tbu_0<= 1'b0;`
345			`selection_tbu_1<= 1'b1;`
346
347			`end`
348			`2'b01:`
349			`begin`
350			`d_in_0_tbu_0 <= d_o_mem_D;`
351			`d_in_1_tbu_0 <= d_o_mem_C;`
352
353			`d_in_0_tbu_1 <= d_o_mem_A;`
354			`d_in_1_tbu_1 <= d_o_mem_D;`
355
356			`selection_tbu_0<= 1'b1;`
357			`selection_tbu_1<= 1'b0;`
358			`end`
359			`2'b10:`
360			`begin`
361			`d_in_0_tbu_0 <= d_o_mem_B;`
362			`d_in_1_tbu_0 <= d_o_mem_A;`
363
364			`d_in_0_tbu_1 <= d_o_mem_A;`
365			`d_in_1_tbu_1 <= d_o_mem_D;`
366
367			`selection_tbu_0<= 1'b0;`
368			`selection_tbu_1<= 1'b1;`
369			`end`
370			`2'b11:`
371			`begin`
372			`d_in_0_tbu_0 <= d_o_mem_B;`
373			`d_in_1_tbu_0 <= d_o_mem_A;`
374
375			`d_in_0_tbu_1 <= d_o_mem_C;`
376			`d_in_1_tbu_1 <= d_o_mem_B;`
377
378			`selection_tbu_0<= 1'b1;`
379			`selection_tbu_1<= 1'b0;`
380			`end`
381			`endcase`
382			`end`
383
384			`//Trace-Back modules instantiation`
385
386			`tbu tbu_0`
387			`(`
388			`.clk(clk),`
389			`.rst(rst),`
390			`.selection(selection_tbu_0),`
391			`.d_in_0(d_in_0_tbu_0),`
392			`.d_in_1(d_in_1_tbu_0),`
393			`.d_o(d_o_tbu_0),`
394			`.wr_en(wr_disp_mem_0)`
395			`);`
396
397			`tbu tbu_1`
398			`(`
399			`.clk(clk),`
400			`.rst(rst),`
401			`.selection(selection_tbu_1),`
402			`.d_in_0(d_in_0_tbu_1),`
403			`.d_in_1(d_in_1_tbu_1),`
404			`.d_o(d_o_tbu_1),`
405			`.wr_en(wr_disp_mem_1)`
406			`);`
407
408			`//Display Memory modules Instantioation`
409
410			`assign d_in_disp_mem_0 = d_o_tbu_0;`
411			`assign d_in_disp_mem_1 = d_o_tbu_1;`
412
413
414			`mem_disp disp_mem_0`
415			`(`
416			`.clk(clk),`
417			`.wr(wr_disp_mem_0),`
418			`.addr(addr_disp_mem_0),`
419			`.d_i(d_in_disp_mem_0),`
420			`.d_o(d_o_disp_mem_0)`
421			`);`
422
423			`mem_disp disp_mem_1`
424			`(`
425			`.clk(clk),`
426			`.wr(wr_disp_mem_1),`
427			`.addr(addr_disp_mem_1),`
428			`.d_i(d_in_disp_mem_1),`
429			`.d_o(d_o_disp_mem_1)`
430			`);`
431
432			`// Display memory module operation`
433			`always @ (posedge clk)`
434			`mem_bank_buf_buf_buf <= mem_bank_buf_buf;`
435
436			`always @ (posedge clk)`
437			`begin`
438			`if(rst==1'b0)`
439			`wr_mem_counter_disp <= 10'b1111111100;`
440			`else`
441			`wr_mem_counter_disp <= wr_mem_counter_disp + 10'd1;`
442			`end`
443
444			`always @ (posedge clk)`
445			`begin`
446			`if(rst==1'b0)`
447			`rd_mem_counter_disp <= 10'b0000000011;`
448			`else`
449			`rd_mem_counter_disp <= rd_mem_counter_disp - 10'd1;`
450			`end`
451
452
453			`always @ (posedge clk)`
454			`begin`
455			`case(mem_bank_buf_buf_buf)`
456			`2'b00:`
457			`begin`
458			`addr_disp_mem_0 <= rd_mem_counter_disp;`
459			`addr_disp_mem_1 <= wr_mem_counter_disp;`
460			`end`
461			`2'b01:`
462			`begin`
463			`addr_disp_mem_0 <= wr_mem_counter_disp;`
464			`addr_disp_mem_1 <= rd_mem_counter_disp;`
465			`end`
466			`2'b10:`
467			`begin`
468			`addr_disp_mem_0 <= rd_mem_counter_disp;`
469			`addr_disp_mem_1 <= wr_mem_counter_disp;`
470			`end`
471			`2'b11:`
472			`begin`
473			`addr_disp_mem_0 <= wr_mem_counter_disp;`
474			`addr_disp_mem_1 <= rd_mem_counter_disp;`
475			`end`
476			`endcase`
477			`end`
478
479			`always @ (posedge clk)`
480			`mem_bank_buf_buf_buf_buf <= mem_bank_buf_buf_buf;`
481
482			`always @ (posedge clk)`
483			`mem_bank_buf_buf_buf_buf_buf <= mem_bank_buf_buf_buf_buf;`
484
485
486
487			`always @ (posedge clk)`
488			`begin`
489			`case(mem_bank_buf_buf_buf_buf_buf)`
490			`2'b00:`
491			`begin`
492			`decoder_o_reg <= d_o_disp_mem_0;`
493			`end`
494			`2'b01:`
495			`begin`
496			`decoder_o_reg <= d_o_disp_mem_1;`
497			`end`
498			`2'b10:`
499			`begin`
500			`decoder_o_reg <= d_o_disp_mem_1;`
501			`end`
502			`2'b11:`
503			`begin`
504			`decoder_o_reg <= d_o_disp_mem_0;`
505			`end`
506			`endcase`
507			`end`
508
509
510			`endmodule`