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Subversion Repositories viterb_encoder_and_decoder

[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [decoder.v] - Blame information for rev 2

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module decoder
(
   clk,
   rst,
   enable,
   d_in,
   d_out
);
 
   input             clk;
   input             rst;
   input             enable;
   input [1:0]       d_in;
   output            d_out;
 
   reg               decoder_o_reg;
 
 
//bmc module signals
   wire  [1:0]       bmc000_path_0_bmc;
   wire  [1:0]       bmc001_path_0_bmc;
   wire  [1:0]       bmc010_path_0_bmc;
   wire  [1:0]       bmc011_path_0_bmc;
   wire  [1:0]       bmc100_path_0_bmc;
   wire  [1:0]       bmc101_path_0_bmc;
   wire  [1:0]       bmc110_path_0_bmc;
   wire  [1:0]       bmc111_path_0_bmc;
 
   wire  [1:0]       bmc000_path_1_bmc;
   wire  [1:0]       bmc001_path_1_bmc;
   wire  [1:0]       bmc010_path_1_bmc;
   wire  [1:0]       bmc011_path_1_bmc;
   wire  [1:0]       bmc100_path_1_bmc;
   wire  [1:0]       bmc101_path_1_bmc;
   wire  [1:0]       bmc110_path_1_bmc;
   wire  [1:0]       bmc111_path_1_bmc;
 
//ACS modules signals
   reg   [7:0]       validity;
   reg   [7:0]       selection;
   reg   [7:0]       path_cost   [7:0];
   wire  [7:0]       validity_nets;
   wire  [7:0]       selection_nets;
 
   wire              ACS000_selection;
   wire              ACS001_selection;
   wire              ACS010_selection;
   wire              ACS011_selection;
   wire              ACS100_selection;
   wire              ACS101_selection;
   wire              ACS110_selection;
   wire              ACS111_selection;
 
   wire              ACS000_valid_o;
   wire              ACS001_valid_o;
   wire              ACS010_valid_o;
   wire              ACS011_valid_o;
   wire              ACS100_valid_o;
   wire              ACS101_valid_o;
   wire              ACS110_valid_o;
   wire              ACS111_valid_o;
 
   wire  [7:0]       ACS000_path_cost;
   wire  [7:0]       ACS001_path_cost;
   wire  [7:0]       ACS010_path_cost;
   wire  [7:0]       ACS011_path_cost;
   wire  [7:0]       ACS100_path_cost;
   wire  [7:0]       ACS101_path_cost;
   wire  [7:0]       ACS110_path_cost;
   wire  [7:0]       ACS111_path_cost;
 
//Trelis memory write operation
   reg   [1:0]       mem_bank;
   reg   [1:0]       mem_bank_buf;
   reg   [1:0]       mem_bank_buf_buf;
   reg               mem_bank_buf_buf_buf;
   reg               mem_bank_buf_buf_buf_buf;
   reg               mem_bank_buf_buf_buf_buf_buf;
   reg   [9:0]       wr_mem_counter;
   reg   [9:0]       rd_mem_counter;
 
   reg   [9:0]       addr_mem_A;
   reg   [9:0]       addr_mem_B;
   reg   [9:0]       addr_mem_C;
   reg   [9:0]       addr_mem_D;
 
   reg               wr_mem_A;
   reg               wr_mem_B;
   reg               wr_mem_C;
   reg               wr_mem_D;
 
   reg   [7:0]       d_in_mem_A;
   reg   [7:0]       d_in_mem_B;
   reg   [7:0]       d_in_mem_C;
   reg   [7:0]       d_in_mem_D;
 
   wire  [7:0]       d_o_mem_A;
   wire  [7:0]       d_o_mem_B;
   wire  [7:0]       d_o_mem_C;
   wire  [7:0]       d_o_mem_D;
 
//Trace back module signals
   reg               selection_tbu_0;
   reg               selection_tbu_1;
 
   reg   [7:0]       d_in_0_tbu_0;
   reg   [7:0]       d_in_1_tbu_0;
   reg   [7:0]       d_in_0_tbu_1;
   reg   [7:0]       d_in_1_tbu_1;
 
   wire              d_o_tbu_0;
   wire              d_o_tbu_1;
 
   reg               enable_tbu_0;
   reg               enable_tbu_1;
 
//Display memory operations 
   wire              wr_disp_mem_0;
   wire              wr_disp_mem_1;
 
   wire              d_in_disp_mem_0;
   wire              d_in_disp_mem_1;
 
   reg   [9:0]       wr_mem_counter_disp;
   reg   [9:0]       rd_mem_counter_disp;
 
   reg   [9:0]       addr_disp_mem_0;
   reg   [9:0]       addr_disp_mem_1;
 
 
   assign   d_out =  decoder_o_reg;
 
 
//Branch matrc calculation modules
 
   bmc000   bmc000_inst(d_in,bmc000_path_0_bmc,bmc000_path_1_bmc);
   bmc001   bmc001_inst(d_in,bmc001_path_0_bmc,bmc001_path_1_bmc);
   bmc010   bmc010_inst(d_in,bmc010_path_0_bmc,bmc010_path_1_bmc);
   bmc011   bmc011_inst(d_in,bmc011_path_0_bmc,bmc011_path_1_bmc);
   bmc100   bmc100_inst(d_in,bmc100_path_0_bmc,bmc100_path_1_bmc);
   bmc101   bmc101_inst(d_in,bmc101_path_0_bmc,bmc101_path_1_bmc);
   bmc110   bmc110_inst(d_in,bmc110_path_0_bmc,bmc110_path_1_bmc);
   bmc111   bmc111_inst(d_in,bmc111_path_0_bmc,bmc111_path_1_bmc);
 
 
//Add Compare Select Modules
 
   ACS      ACS000(validity[0],validity[1],bmc000_path_0_bmc,bmc000_path_1_bmc,path_cost[0],path_cost[1],ACS000_selection,ACS000_valid_o,ACS000_path_cost);
   ACS      ACS001(validity[3],validity[2],bmc001_path_0_bmc,bmc001_path_1_bmc,path_cost[3],path_cost[2],ACS001_selection,ACS001_valid_o,ACS001_path_cost);
   ACS      ACS010(validity[4],validity[5],bmc010_path_0_bmc,bmc010_path_1_bmc,path_cost[4],path_cost[5],ACS010_selection,ACS010_valid_o,ACS010_path_cost);
   ACS      ACS011(validity[7],validity[6],bmc011_path_0_bmc,bmc011_path_1_bmc,path_cost[7],path_cost[6],ACS011_selection,ACS011_valid_o,ACS011_path_cost);
   ACS      ACS100(validity[1],validity[0],bmc100_path_0_bmc,bmc100_path_1_bmc,path_cost[1],path_cost[0],ACS100_selection,ACS100_valid_o,ACS100_path_cost);
   ACS      ACS101(validity[2],validity[3],bmc101_path_0_bmc,bmc101_path_1_bmc,path_cost[2],path_cost[3],ACS101_selection,ACS101_valid_o,ACS101_path_cost);
   ACS      ACS110(validity[5],validity[4],bmc110_path_0_bmc,bmc110_path_1_bmc,path_cost[5],path_cost[4],ACS110_selection,ACS110_valid_o,ACS110_path_cost);
   ACS      ACS111(validity[6],validity[7],bmc111_path_0_bmc,bmc111_path_1_bmc,path_cost[6],path_cost[7],ACS111_selection,ACS111_valid_o,ACS111_path_cost);
 
 
   assign selection_nets  =  {ACS111_selection,ACS110_selection,ACS101_selection,ACS100_selection,
                              ACS011_selection,ACS010_selection,ACS001_selection,ACS000_selection};
   assign validity_nets    =  {ACS111_valid_o,ACS110_valid_o,ACS101_valid_o,ACS100_valid_o,
                              ACS011_valid_o,ACS010_valid_o,ACS001_valid_o,ACS000_valid_o};
 
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
      begin
         validity          <= 8'b00000001;
         selection         <= 8'b00000000;
 
         path_cost[0]      <= 8'd0;
         path_cost[1]      <= 8'd0;
         path_cost[2]      <= 8'd0;
         path_cost[3]      <= 8'd0;
         path_cost[4]      <= 8'd0;
         path_cost[5]      <= 8'd0;
         path_cost[6]      <= 8'd0;
         path_cost[7]      <= 8'd0;
 
      end
      else if(enable==1'b0)
      begin
         validity          <= 8'b00000001;
         selection         <= 8'b00000000;
 
         path_cost[0]      <= 8'd0;
         path_cost[1]      <= 8'd0;
         path_cost[2]      <= 8'd0;
         path_cost[3]      <= 8'd0;
         path_cost[4]      <= 8'd0;
         path_cost[5]      <= 8'd0;
         path_cost[6]      <= 8'd0;
         path_cost[7]      <= 8'd0;
 
      end
      else if( path_cost[0][7] && path_cost[1][7] && path_cost[2][7] && path_cost[3][7] &&
             path_cost[4][7] && path_cost[5][7] && path_cost[6][7] && path_cost[7][7] )
      begin
 
         validity          <= validity_nets;
         selection         <= selection_nets;
 
         path_cost[0]      <= 8'b01111111 & ACS000_path_cost;
         path_cost[1]      <= 8'b01111111 & ACS001_path_cost;
         path_cost[2]      <= 8'b01111111 & ACS010_path_cost;
         path_cost[3]      <= 8'b01111111 & ACS011_path_cost;
         path_cost[4]      <= 8'b01111111 & ACS100_path_cost;
         path_cost[5]      <= 8'b01111111 & ACS101_path_cost;
         path_cost[6]      <= 8'b01111111 & ACS110_path_cost;
         path_cost[7]      <= 8'b01111111 & ACS111_path_cost;
      end
      else
      begin
         validity          <= validity_nets;
         selection         <= selection_nets;
 
         path_cost[0]      <= ACS000_path_cost;
         path_cost[1]      <= ACS001_path_cost;
         path_cost[2]      <= ACS010_path_cost;
         path_cost[3]      <= ACS011_path_cost;
         path_cost[4]      <= ACS100_path_cost;
         path_cost[5]      <= ACS101_path_cost;
         path_cost[6]      <= ACS110_path_cost;
         path_cost[7]      <= ACS111_path_cost;
      end
   end
 
 
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
         wr_mem_counter <= 10'd0;
      else if(enable==1'b0)
         wr_mem_counter <= 10'd0;
      else
         wr_mem_counter <= wr_mem_counter + 10'd1;
   end
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
         rd_mem_counter <= 10'b1111111111;
      else if(enable==1'b0)
         wr_mem_counter <= 10'd0;
      else
         rd_mem_counter <= rd_mem_counter - 10'd1;
   end
 
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
         mem_bank <= 2'b00;
      else begin
         if(wr_mem_counter==10'b1111111111)
               mem_bank <= mem_bank + 2'b01;
      end
   end
 
 
   always @ (posedge clk)
   begin
      d_in_mem_A  <= selection;
      d_in_mem_B  <= selection;
      d_in_mem_C  <= selection;
      d_in_mem_D  <= selection;
 
   end
 
 
   always @ (posedge clk)
   begin
      case(mem_bank)
         2'b00:
         begin
            addr_mem_A        <= wr_mem_counter;
            addr_mem_B        <= rd_mem_counter;
            addr_mem_C        <= 10'd0;
            addr_mem_D        <= rd_mem_counter;
 
            wr_mem_A          <= 1'b1;
            wr_mem_B          <= 1'b0;
            wr_mem_C          <= 1'b0;
            wr_mem_D          <= 1'b0;
         end
         2'b01:
         begin
            addr_mem_A        <= rd_mem_counter;
            addr_mem_B        <= wr_mem_counter;
            addr_mem_C        <= rd_mem_counter;
            addr_mem_D        <= 10'd0;
 
            wr_mem_A          <= 1'b0;
            wr_mem_B          <= 1'b1;
            wr_mem_C          <= 1'b0;
            wr_mem_D          <= 1'b0;
 
         end
         2'b10:
         begin
            addr_mem_A        <= 10'd0;
            addr_mem_B        <= rd_mem_counter;
            addr_mem_C        <= wr_mem_counter;
            addr_mem_D        <= rd_mem_counter;
 
            wr_mem_A          <= 1'b0;
            wr_mem_B          <= 1'b0;
            wr_mem_C          <= 1'b1;
            wr_mem_D          <= 1'b0;
         end
         2'b11:
         begin
            addr_mem_A        <= rd_mem_counter;
            addr_mem_B        <= 10'd0;
            addr_mem_C        <= rd_mem_counter;
            addr_mem_D        <= wr_mem_counter;
 
            wr_mem_A          <= 1'b0;
            wr_mem_B          <= 1'b0;
            wr_mem_C          <= 1'b0;
            wr_mem_D          <= 1'b1;
         end
      endcase
  end
 
//Trelis memory module instantiation
 
   mem   trelis_mem_A
   (
      .clk(clk),
      .wr(wr_mem_A),
      .addr(addr_mem_A),
      .d_i(d_in_mem_A),
      .d_o(d_o_mem_A)
   );
 
  mem   trelis_mem_B
   (
      .clk(clk),
      .wr(wr_mem_B),
      .addr(addr_mem_B),
      .d_i(d_in_mem_B),
      .d_o(d_o_mem_B)
   );
 
  mem   trelis_mem_C
   (
      .clk(clk),
      .wr(wr_mem_C),
      .addr(addr_mem_C),
      .d_i(d_in_mem_C),
      .d_o(d_o_mem_C)
   );
 
  mem   trelis_mem_D
   (
      .clk(clk),
      .wr(wr_mem_D),
      .addr(addr_mem_D),
      .d_i(d_in_mem_D),
      .d_o(d_o_mem_D)
   );
 
//Trace back module operation
 
   always @(posedge clk)
      mem_bank_buf   <= mem_bank;
 
   always @(posedge clk)
      mem_bank_buf_buf   <= mem_bank_buf;
 
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
            enable_tbu_0   <= 1'b0;
      else begin
         if(mem_bank_buf_buf==2'b10)
            enable_tbu_0   <= 1'b1;
         else
            enable_tbu_0   <= enable_tbu_0;
      end
   end
 
   always @ (posedge clk or negedge rst)
   begin
      if(rst==1'b0)
            enable_tbu_1   <= 1'b0;
      else begin
         if(mem_bank_buf_buf==2'b11)
            enable_tbu_1   <= 1'b1;
         else
            enable_tbu_1   <= enable_tbu_1;
      end
   end
 
   always @ (posedge clk)
   begin
      case(mem_bank_buf_buf)
         2'b00:
         begin
            d_in_0_tbu_0   <= d_o_mem_D;
            d_in_1_tbu_0   <= d_o_mem_C;
 
            d_in_0_tbu_1   <= d_o_mem_C;
            d_in_1_tbu_1   <= d_o_mem_B;
 
            selection_tbu_0<= 1'b0;
            selection_tbu_1<= 1'b1;
 
         end
         2'b01:
         begin
            d_in_0_tbu_0   <= d_o_mem_D;
            d_in_1_tbu_0   <= d_o_mem_C;
 
            d_in_0_tbu_1   <= d_o_mem_A;
            d_in_1_tbu_1   <= d_o_mem_D;
 
            selection_tbu_0<= 1'b1;
            selection_tbu_1<= 1'b0;
         end
         2'b10:
         begin
            d_in_0_tbu_0   <= d_o_mem_B;
            d_in_1_tbu_0   <= d_o_mem_A;
 
            d_in_0_tbu_1   <= d_o_mem_A;
            d_in_1_tbu_1   <= d_o_mem_D;
 
            selection_tbu_0<= 1'b0;
            selection_tbu_1<= 1'b1;
         end
         2'b11:
         begin
            d_in_0_tbu_0   <= d_o_mem_B;
            d_in_1_tbu_0   <= d_o_mem_A;
 
            d_in_0_tbu_1   <= d_o_mem_C;
            d_in_1_tbu_1   <= d_o_mem_B;
 
            selection_tbu_0<= 1'b1;
            selection_tbu_1<= 1'b0;
         end
      endcase
   end
 
//Trace-Back modules instantiation
 
   tbu tbu_0
   (
      .clk(clk),
      .rst(rst),
      .enable(enable_tbu_0),
      .selection(selection_tbu_0),
      .d_in_0(d_in_0_tbu_0),
      .d_in_1(d_in_1_tbu_0),
      .d_o(d_o_tbu_0),
      .wr_en(wr_disp_mem_0)
   );
 
   tbu tbu_1
   (
      .clk(clk),
      .rst(rst),
      .enable(enable_tbu_1),
      .selection(selection_tbu_1),
      .d_in_0(d_in_0_tbu_1),
      .d_in_1(d_in_1_tbu_1),
      .d_o(d_o_tbu_1),
      .wr_en(wr_disp_mem_1)
   );
 
//Display Memory modules Instantioation
 
   assign   d_in_disp_mem_0   =  d_o_tbu_0;
   assign   d_in_disp_mem_1   =  d_o_tbu_1;
 
 
  mem_disp   disp_mem_0
  (
      .clk(clk),
      .wr(wr_disp_mem_0),
      .addr(addr_disp_mem_0),
      .d_i(d_in_disp_mem_0),
      .d_o(d_o_disp_mem_0)
   );
 
  mem_disp   disp_mem_1
  (
      .clk(clk),
      .wr(wr_disp_mem_1),
      .addr(addr_disp_mem_1),
      .d_i(d_in_disp_mem_1),
      .d_o(d_o_disp_mem_1)
   );
 
// Display memory module operation
   always @ (posedge clk)
      mem_bank_buf_buf_buf <= mem_bank_buf_buf[0];
 
   always @ (posedge clk)
   begin
      if(rst==1'b0)
         wr_mem_counter_disp  <= 10'b0000000010;
      if(enable==1'b0)
         wr_mem_counter_disp  <= 10'b0000000010;
      else
         wr_mem_counter_disp  <= wr_mem_counter_disp - 10'd1;
   end
 
   always @ (posedge clk)
   begin
      if(rst==1'b0)
         rd_mem_counter_disp  <= 10'b1111111101;
      if(enable==1'b0)
         rd_mem_counter_disp  <= 10'b1111111101;
      else
         rd_mem_counter_disp  <= rd_mem_counter_disp + 10'd1;
   end
 
 
   always @ (posedge clk)
   begin
      case(mem_bank_buf_buf_buf)
         1'b0:
         begin
            addr_disp_mem_0   <= rd_mem_counter_disp;
            addr_disp_mem_1   <= wr_mem_counter_disp;
         end
         1'b1:
         begin
            addr_disp_mem_0   <= wr_mem_counter_disp;
            addr_disp_mem_1   <= rd_mem_counter_disp;
         end
      endcase
   end
 
 
   always @ (posedge clk)
      mem_bank_buf_buf_buf_buf   <= mem_bank_buf_buf_buf;
 
   always @ (posedge clk)
      mem_bank_buf_buf_buf_buf_buf <= mem_bank_buf_buf_buf_buf;
 
 
 
   always @ (posedge clk)
   begin
      case(mem_bank_buf_buf_buf_buf_buf)
         1'b0:
         begin
            decoder_o_reg  <= d_o_disp_mem_0;
         end
         1'b1:
         begin
            decoder_o_reg  <= d_o_disp_mem_1;
         end
      endcase
   end
 
endmodule

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Subversion Repositories viterb_encoder_and_decoder

[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [decoder.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sandunrath	`module decoder`
2			`(`
3			`clk,`
4			`rst,`
5			`enable,`
6			`d_in,`
7			`d_out`
8			`);`
9
10			`input clk;`
11			`input rst;`
12			`input enable;`
13			`input [1:0] d_in;`
14			`output d_out;`
15
16			`reg decoder_o_reg;`
17
18
19			`//bmc module signals`
20			`wire [1:0] bmc000_path_0_bmc;`
21			`wire [1:0] bmc001_path_0_bmc;`
22			`wire [1:0] bmc010_path_0_bmc;`
23			`wire [1:0] bmc011_path_0_bmc;`
24			`wire [1:0] bmc100_path_0_bmc;`
25			`wire [1:0] bmc101_path_0_bmc;`
26			`wire [1:0] bmc110_path_0_bmc;`
27			`wire [1:0] bmc111_path_0_bmc;`
28
29			`wire [1:0] bmc000_path_1_bmc;`
30			`wire [1:0] bmc001_path_1_bmc;`
31			`wire [1:0] bmc010_path_1_bmc;`
32			`wire [1:0] bmc011_path_1_bmc;`
33			`wire [1:0] bmc100_path_1_bmc;`
34			`wire [1:0] bmc101_path_1_bmc;`
35			`wire [1:0] bmc110_path_1_bmc;`
36			`wire [1:0] bmc111_path_1_bmc;`
37
38			`//ACS modules signals`
39			`reg [7:0] validity;`
40			`reg [7:0] selection;`
41			`reg [7:0] path_cost [7:0];`
42			`wire [7:0] validity_nets;`
43			`wire [7:0] selection_nets;`
44
45			`wire ACS000_selection;`
46			`wire ACS001_selection;`
47			`wire ACS010_selection;`
48			`wire ACS011_selection;`
49			`wire ACS100_selection;`
50			`wire ACS101_selection;`
51			`wire ACS110_selection;`
52			`wire ACS111_selection;`
53
54			`wire ACS000_valid_o;`
55			`wire ACS001_valid_o;`
56			`wire ACS010_valid_o;`
57			`wire ACS011_valid_o;`
58			`wire ACS100_valid_o;`
59			`wire ACS101_valid_o;`
60			`wire ACS110_valid_o;`
61			`wire ACS111_valid_o;`
62
63			`wire [7:0] ACS000_path_cost;`
64			`wire [7:0] ACS001_path_cost;`
65			`wire [7:0] ACS010_path_cost;`
66			`wire [7:0] ACS011_path_cost;`
67			`wire [7:0] ACS100_path_cost;`
68			`wire [7:0] ACS101_path_cost;`
69			`wire [7:0] ACS110_path_cost;`
70			`wire [7:0] ACS111_path_cost;`
71
72			`//Trelis memory write operation`
73			`reg [1:0] mem_bank;`
74			`reg [1:0] mem_bank_buf;`
75			`reg [1:0] mem_bank_buf_buf;`
76			`reg mem_bank_buf_buf_buf;`
77			`reg mem_bank_buf_buf_buf_buf;`
78			`reg mem_bank_buf_buf_buf_buf_buf;`
79			`reg [9:0] wr_mem_counter;`
80			`reg [9:0] rd_mem_counter;`
81
82			`reg [9:0] addr_mem_A;`
83			`reg [9:0] addr_mem_B;`
84			`reg [9:0] addr_mem_C;`
85			`reg [9:0] addr_mem_D;`
86
87			`reg wr_mem_A;`
88			`reg wr_mem_B;`
89			`reg wr_mem_C;`
90			`reg wr_mem_D;`
91
92			`reg [7:0] d_in_mem_A;`
93			`reg [7:0] d_in_mem_B;`
94			`reg [7:0] d_in_mem_C;`
95			`reg [7:0] d_in_mem_D;`
96
97			`wire [7:0] d_o_mem_A;`
98			`wire [7:0] d_o_mem_B;`
99			`wire [7:0] d_o_mem_C;`
100			`wire [7:0] d_o_mem_D;`
101
102			`//Trace back module signals`
103			`reg selection_tbu_0;`
104			`reg selection_tbu_1;`
105
106			`reg [7:0] d_in_0_tbu_0;`
107			`reg [7:0] d_in_1_tbu_0;`
108			`reg [7:0] d_in_0_tbu_1;`
109			`reg [7:0] d_in_1_tbu_1;`
110
111			`wire d_o_tbu_0;`
112			`wire d_o_tbu_1;`
113
114			`reg enable_tbu_0;`
115			`reg enable_tbu_1;`
116
117			`//Display memory operations`
118			`wire wr_disp_mem_0;`
119			`wire wr_disp_mem_1;`
120
121			`wire d_in_disp_mem_0;`
122			`wire d_in_disp_mem_1;`
123
124			`reg [9:0] wr_mem_counter_disp;`
125			`reg [9:0] rd_mem_counter_disp;`
126
127			`reg [9:0] addr_disp_mem_0;`
128			`reg [9:0] addr_disp_mem_1;`
129
130
131			`assign d_out = decoder_o_reg;`
132
133
134			`//Branch matrc calculation modules`
135
136			`bmc000 bmc000_inst(d_in,bmc000_path_0_bmc,bmc000_path_1_bmc);`
137			`bmc001 bmc001_inst(d_in,bmc001_path_0_bmc,bmc001_path_1_bmc);`
138			`bmc010 bmc010_inst(d_in,bmc010_path_0_bmc,bmc010_path_1_bmc);`
139			`bmc011 bmc011_inst(d_in,bmc011_path_0_bmc,bmc011_path_1_bmc);`
140			`bmc100 bmc100_inst(d_in,bmc100_path_0_bmc,bmc100_path_1_bmc);`
141			`bmc101 bmc101_inst(d_in,bmc101_path_0_bmc,bmc101_path_1_bmc);`
142			`bmc110 bmc110_inst(d_in,bmc110_path_0_bmc,bmc110_path_1_bmc);`
143			`bmc111 bmc111_inst(d_in,bmc111_path_0_bmc,bmc111_path_1_bmc);`
144
145
146			`//Add Compare Select Modules`
147
148			`ACS ACS000(validity[0],validity[1],bmc000_path_0_bmc,bmc000_path_1_bmc,path_cost[0],path_cost[1],ACS000_selection,ACS000_valid_o,ACS000_path_cost);`
149			`ACS ACS001(validity[3],validity[2],bmc001_path_0_bmc,bmc001_path_1_bmc,path_cost[3],path_cost[2],ACS001_selection,ACS001_valid_o,ACS001_path_cost);`
150			`ACS ACS010(validity[4],validity[5],bmc010_path_0_bmc,bmc010_path_1_bmc,path_cost[4],path_cost[5],ACS010_selection,ACS010_valid_o,ACS010_path_cost);`
151			`ACS ACS011(validity[7],validity[6],bmc011_path_0_bmc,bmc011_path_1_bmc,path_cost[7],path_cost[6],ACS011_selection,ACS011_valid_o,ACS011_path_cost);`
152			`ACS ACS100(validity[1],validity[0],bmc100_path_0_bmc,bmc100_path_1_bmc,path_cost[1],path_cost[0],ACS100_selection,ACS100_valid_o,ACS100_path_cost);`
153			`ACS ACS101(validity[2],validity[3],bmc101_path_0_bmc,bmc101_path_1_bmc,path_cost[2],path_cost[3],ACS101_selection,ACS101_valid_o,ACS101_path_cost);`
154			`ACS ACS110(validity[5],validity[4],bmc110_path_0_bmc,bmc110_path_1_bmc,path_cost[5],path_cost[4],ACS110_selection,ACS110_valid_o,ACS110_path_cost);`
155			`ACS ACS111(validity[6],validity[7],bmc111_path_0_bmc,bmc111_path_1_bmc,path_cost[6],path_cost[7],ACS111_selection,ACS111_valid_o,ACS111_path_cost);`
156
157
158			`assign selection_nets = {ACS111_selection,ACS110_selection,ACS101_selection,ACS100_selection,`
159			`ACS011_selection,ACS010_selection,ACS001_selection,ACS000_selection};`
160			`assign validity_nets = {ACS111_valid_o,ACS110_valid_o,ACS101_valid_o,ACS100_valid_o,`
161			`ACS011_valid_o,ACS010_valid_o,ACS001_valid_o,ACS000_valid_o};`
162
163
164			`always @ (posedge clk or negedge rst)`
165			`begin`
166			`if(rst==1'b0)`
167			`begin`
168			`validity <= 8'b00000001;`
169			`selection <= 8'b00000000;`
170
171			`path_cost[0] <= 8'd0;`
172			`path_cost[1] <= 8'd0;`
173			`path_cost[2] <= 8'd0;`
174			`path_cost[3] <= 8'd0;`
175			`path_cost[4] <= 8'd0;`
176			`path_cost[5] <= 8'd0;`
177			`path_cost[6] <= 8'd0;`
178			`path_cost[7] <= 8'd0;`
179
180			`end`
181			`else if(enable==1'b0)`
182			`begin`
183			`validity <= 8'b00000001;`
184			`selection <= 8'b00000000;`
185
186			`path_cost[0] <= 8'd0;`
187			`path_cost[1] <= 8'd0;`
188			`path_cost[2] <= 8'd0;`
189			`path_cost[3] <= 8'd0;`
190			`path_cost[4] <= 8'd0;`
191			`path_cost[5] <= 8'd0;`
192			`path_cost[6] <= 8'd0;`
193			`path_cost[7] <= 8'd0;`
194
195			`end`
196			`else if( path_cost[0][7] && path_cost[1][7] && path_cost[2][7] && path_cost[3][7] &&`
197			`path_cost[4][7] && path_cost[5][7] && path_cost[6][7] && path_cost[7][7] )`
198			`begin`
199
200			`validity <= validity_nets;`
201			`selection <= selection_nets;`
202
203			`path_cost[0] <= 8'b01111111 & ACS000_path_cost;`
204			`path_cost[1] <= 8'b01111111 & ACS001_path_cost;`
205			`path_cost[2] <= 8'b01111111 & ACS010_path_cost;`
206			`path_cost[3] <= 8'b01111111 & ACS011_path_cost;`
207			`path_cost[4] <= 8'b01111111 & ACS100_path_cost;`
208			`path_cost[5] <= 8'b01111111 & ACS101_path_cost;`
209			`path_cost[6] <= 8'b01111111 & ACS110_path_cost;`
210			`path_cost[7] <= 8'b01111111 & ACS111_path_cost;`
211			`end`
212			`else`
213			`begin`
214			`validity <= validity_nets;`
215			`selection <= selection_nets;`
216
217			`path_cost[0] <= ACS000_path_cost;`
218			`path_cost[1] <= ACS001_path_cost;`
219			`path_cost[2] <= ACS010_path_cost;`
220			`path_cost[3] <= ACS011_path_cost;`
221			`path_cost[4] <= ACS100_path_cost;`
222			`path_cost[5] <= ACS101_path_cost;`
223			`path_cost[6] <= ACS110_path_cost;`
224			`path_cost[7] <= ACS111_path_cost;`
225			`end`
226			`end`
227
228
229
230			`always @ (posedge clk or negedge rst)`
231			`begin`
232			`if(rst==1'b0)`
233			`wr_mem_counter <= 10'd0;`
234			`else if(enable==1'b0)`
235			`wr_mem_counter <= 10'd0;`
236			`else`
237			`wr_mem_counter <= wr_mem_counter + 10'd1;`
238			`end`
239
240			`always @ (posedge clk or negedge rst)`
241			`begin`
242			`if(rst==1'b0)`
243			`rd_mem_counter <= 10'b1111111111;`
244			`else if(enable==1'b0)`
245			`wr_mem_counter <= 10'd0;`
246			`else`
247			`rd_mem_counter <= rd_mem_counter - 10'd1;`
248			`end`
249
250
251			`always @ (posedge clk or negedge rst)`
252			`begin`
253			`if(rst==1'b0)`
254			`mem_bank <= 2'b00;`
255			`else begin`
256			`if(wr_mem_counter==10'b1111111111)`
257			`mem_bank <= mem_bank + 2'b01;`
258			`end`
259			`end`
260
261
262			`always @ (posedge clk)`
263			`begin`
264			`d_in_mem_A <= selection;`
265			`d_in_mem_B <= selection;`
266			`d_in_mem_C <= selection;`
267			`d_in_mem_D <= selection;`
268
269			`end`
270
271
272			`always @ (posedge clk)`
273			`begin`
274			`case(mem_bank)`
275			`2'b00:`
276			`begin`
277			`addr_mem_A <= wr_mem_counter;`
278			`addr_mem_B <= rd_mem_counter;`
279			`addr_mem_C <= 10'd0;`
280			`addr_mem_D <= rd_mem_counter;`
281
282			`wr_mem_A <= 1'b1;`
283			`wr_mem_B <= 1'b0;`
284			`wr_mem_C <= 1'b0;`
285			`wr_mem_D <= 1'b0;`
286			`end`
287			`2'b01:`
288			`begin`
289			`addr_mem_A <= rd_mem_counter;`
290			`addr_mem_B <= wr_mem_counter;`
291			`addr_mem_C <= rd_mem_counter;`
292			`addr_mem_D <= 10'd0;`
293
294			`wr_mem_A <= 1'b0;`
295			`wr_mem_B <= 1'b1;`
296			`wr_mem_C <= 1'b0;`
297			`wr_mem_D <= 1'b0;`
298
299			`end`
300			`2'b10:`
301			`begin`
302			`addr_mem_A <= 10'd0;`
303			`addr_mem_B <= rd_mem_counter;`
304			`addr_mem_C <= wr_mem_counter;`
305			`addr_mem_D <= rd_mem_counter;`
306
307			`wr_mem_A <= 1'b0;`
308			`wr_mem_B <= 1'b0;`
309			`wr_mem_C <= 1'b1;`
310			`wr_mem_D <= 1'b0;`
311			`end`
312			`2'b11:`
313			`begin`
314			`addr_mem_A <= rd_mem_counter;`
315			`addr_mem_B <= 10'd0;`
316			`addr_mem_C <= rd_mem_counter;`
317			`addr_mem_D <= wr_mem_counter;`
318
319			`wr_mem_A <= 1'b0;`
320			`wr_mem_B <= 1'b0;`
321			`wr_mem_C <= 1'b0;`
322			`wr_mem_D <= 1'b1;`
323			`end`
324			`endcase`
325			`end`
326
327			`//Trelis memory module instantiation`
328
329			`mem trelis_mem_A`
330			`(`
331			`.clk(clk),`
332			`.wr(wr_mem_A),`
333			`.addr(addr_mem_A),`
334			`.d_i(d_in_mem_A),`
335			`.d_o(d_o_mem_A)`
336			`);`
337
338			`mem trelis_mem_B`
339			`(`
340			`.clk(clk),`
341			`.wr(wr_mem_B),`
342			`.addr(addr_mem_B),`
343			`.d_i(d_in_mem_B),`
344			`.d_o(d_o_mem_B)`
345			`);`
346
347			`mem trelis_mem_C`
348			`(`
349			`.clk(clk),`
350			`.wr(wr_mem_C),`
351			`.addr(addr_mem_C),`
352			`.d_i(d_in_mem_C),`
353			`.d_o(d_o_mem_C)`
354			`);`
355
356			`mem trelis_mem_D`
357			`(`
358			`.clk(clk),`
359			`.wr(wr_mem_D),`
360			`.addr(addr_mem_D),`
361			`.d_i(d_in_mem_D),`
362			`.d_o(d_o_mem_D)`
363			`);`
364
365			`//Trace back module operation`
366
367			`always @(posedge clk)`
368			`mem_bank_buf <= mem_bank;`
369
370			`always @(posedge clk)`
371			`mem_bank_buf_buf <= mem_bank_buf;`
372
373
374			`always @ (posedge clk or negedge rst)`
375			`begin`
376			`if(rst==1'b0)`
377			`enable_tbu_0 <= 1'b0;`
378			`else begin`
379			`if(mem_bank_buf_buf==2'b10)`
380			`enable_tbu_0 <= 1'b1;`
381			`else`
382			`enable_tbu_0 <= enable_tbu_0;`
383			`end`
384			`end`
385
386			`always @ (posedge clk or negedge rst)`
387			`begin`
388			`if(rst==1'b0)`
389			`enable_tbu_1 <= 1'b0;`
390			`else begin`
391			`if(mem_bank_buf_buf==2'b11)`
392			`enable_tbu_1 <= 1'b1;`
393			`else`
394			`enable_tbu_1 <= enable_tbu_1;`
395			`end`
396			`end`
397
398			`always @ (posedge clk)`
399			`begin`
400			`case(mem_bank_buf_buf)`
401			`2'b00:`
402			`begin`
403			`d_in_0_tbu_0 <= d_o_mem_D;`
404			`d_in_1_tbu_0 <= d_o_mem_C;`
405
406			`d_in_0_tbu_1 <= d_o_mem_C;`
407			`d_in_1_tbu_1 <= d_o_mem_B;`
408
409			`selection_tbu_0<= 1'b0;`
410			`selection_tbu_1<= 1'b1;`
411
412			`end`
413			`2'b01:`
414			`begin`
415			`d_in_0_tbu_0 <= d_o_mem_D;`
416			`d_in_1_tbu_0 <= d_o_mem_C;`
417
418			`d_in_0_tbu_1 <= d_o_mem_A;`
419			`d_in_1_tbu_1 <= d_o_mem_D;`
420
421			`selection_tbu_0<= 1'b1;`
422			`selection_tbu_1<= 1'b0;`
423			`end`
424			`2'b10:`
425			`begin`
426			`d_in_0_tbu_0 <= d_o_mem_B;`
427			`d_in_1_tbu_0 <= d_o_mem_A;`
428
429			`d_in_0_tbu_1 <= d_o_mem_A;`
430			`d_in_1_tbu_1 <= d_o_mem_D;`
431
432			`selection_tbu_0<= 1'b0;`
433			`selection_tbu_1<= 1'b1;`
434			`end`
435			`2'b11:`
436			`begin`
437			`d_in_0_tbu_0 <= d_o_mem_B;`
438			`d_in_1_tbu_0 <= d_o_mem_A;`
439
440			`d_in_0_tbu_1 <= d_o_mem_C;`
441			`d_in_1_tbu_1 <= d_o_mem_B;`
442
443			`selection_tbu_0<= 1'b1;`
444			`selection_tbu_1<= 1'b0;`
445			`end`
446			`endcase`
447			`end`
448
449			`//Trace-Back modules instantiation`
450
451			`tbu tbu_0`
452			`(`
453			`.clk(clk),`
454			`.rst(rst),`
455			`.enable(enable_tbu_0),`
456			`.selection(selection_tbu_0),`
457			`.d_in_0(d_in_0_tbu_0),`
458			`.d_in_1(d_in_1_tbu_0),`
459			`.d_o(d_o_tbu_0),`
460			`.wr_en(wr_disp_mem_0)`
461			`);`
462
463			`tbu tbu_1`
464			`(`
465			`.clk(clk),`
466			`.rst(rst),`
467			`.enable(enable_tbu_1),`
468			`.selection(selection_tbu_1),`
469			`.d_in_0(d_in_0_tbu_1),`
470			`.d_in_1(d_in_1_tbu_1),`
471			`.d_o(d_o_tbu_1),`
472			`.wr_en(wr_disp_mem_1)`
473			`);`
474
475			`//Display Memory modules Instantioation`
476
477			`assign d_in_disp_mem_0 = d_o_tbu_0;`
478			`assign d_in_disp_mem_1 = d_o_tbu_1;`
479
480
481			`mem_disp disp_mem_0`
482			`(`
483			`.clk(clk),`
484			`.wr(wr_disp_mem_0),`
485			`.addr(addr_disp_mem_0),`
486			`.d_i(d_in_disp_mem_0),`
487			`.d_o(d_o_disp_mem_0)`
488			`);`
489
490			`mem_disp disp_mem_1`
491			`(`
492			`.clk(clk),`
493			`.wr(wr_disp_mem_1),`
494			`.addr(addr_disp_mem_1),`
495			`.d_i(d_in_disp_mem_1),`
496			`.d_o(d_o_disp_mem_1)`
497			`);`
498
499			`// Display memory module operation`
500			`always @ (posedge clk)`
501			`mem_bank_buf_buf_buf <= mem_bank_buf_buf[0];`
502
503			`always @ (posedge clk)`
504			`begin`
505			`if(rst==1'b0)`
506			`wr_mem_counter_disp <= 10'b0000000010;`
507			`if(enable==1'b0)`
508			`wr_mem_counter_disp <= 10'b0000000010;`
509			`else`
510			`wr_mem_counter_disp <= wr_mem_counter_disp - 10'd1;`
511			`end`
512
513			`always @ (posedge clk)`
514			`begin`
515			`if(rst==1'b0)`
516			`rd_mem_counter_disp <= 10'b1111111101;`
517			`if(enable==1'b0)`
518			`rd_mem_counter_disp <= 10'b1111111101;`
519			`else`
520			`rd_mem_counter_disp <= rd_mem_counter_disp + 10'd1;`
521			`end`
522
523
524			`always @ (posedge clk)`
525			`begin`
526			`case(mem_bank_buf_buf_buf)`
527			`1'b0:`
528			`begin`
529			`addr_disp_mem_0 <= rd_mem_counter_disp;`
530			`addr_disp_mem_1 <= wr_mem_counter_disp;`
531			`end`
532			`1'b1:`
533			`begin`
534			`addr_disp_mem_0 <= wr_mem_counter_disp;`
535			`addr_disp_mem_1 <= rd_mem_counter_disp;`
536			`end`
537			`endcase`
538			`end`
539
540
541			`always @ (posedge clk)`
542			`mem_bank_buf_buf_buf_buf <= mem_bank_buf_buf_buf;`
543
544			`always @ (posedge clk)`
545			`mem_bank_buf_buf_buf_buf_buf <= mem_bank_buf_buf_buf_buf;`
546
547
548
549			`always @ (posedge clk)`
550			`begin`
551			`case(mem_bank_buf_buf_buf_buf_buf)`
552			`1'b0:`
553			`begin`
554			`decoder_o_reg <= d_o_disp_mem_0;`
555			`end`
556			`1'b1:`
557			`begin`
558			`decoder_o_reg <= d_o_disp_mem_1;`
559			`end`
560			`endcase`
561			`end`
562
563			`endmodule`