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[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [encoder.v] - Blame information for rev 2

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module encoder
(
   clk,
   rst,
   enable_i,
   d_in,
   valid_o,
   d_out
);
   input             clk;
   input             rst;
   input             enable_i;
   input             d_in;
   output reg        valid_o;
   output      [1:0] d_out;
 
   reg         [2:0] cstate;
   reg         [2:0] nstate;
 
   reg         [1:0] d_out_reg;
 
   assign   d_out    =  (enable_i==1'b1)?d_out_reg:2'b00;
 
 
   always @(*) begin
      valid_o  =   enable_i;
      case (cstate)
         3'b000:
         begin
            if(d_in==1'b0)
            begin
               nstate   =  3'b000;
               d_out_reg    =  2'b00;
            end
            else
            begin
               nstate   =  3'b100;
               d_out_reg    =  2'b11;
            end
         end
         3'b001:
         begin
            if(d_in==1'b0)
            begin
               nstate   =  3'b100;
               d_out_reg    =  2'b00;
            end
            else
            begin
               nstate   =  3'b000;
               d_out_reg    =  2'b11;
            end
         end
         3'b010:
         begin
            if(d_in==1'b0)
            begin
               nstate   =  3'b101;
               d_out_reg    =  2'b10;
            end
            else
            begin
               nstate   =  3'b001;
               d_out_reg    =  2'b01;
            end
         end
         3'b011:
         begin
            if(d_in==1'b0)
            begin
               nstate   =  3'b001;
               d_out_reg    =  2'b10;
            end
            else
            begin
               nstate   =  3'b101;
               d_out_reg    =  2'b01;
            end
         end
         3'b100:
         begin
            if(d_in==1'b0)
            begin
               nstate   =  3'b010;
               d_out_reg    =  2'b10;
            end
            else
            begin
               nstate   =  3'b110;
               d_out_reg    =  2'b01;
            end
         end
         3'b101:
         begin
            if(d_in==1'b0)
            begin
               nstate   =  3'b110;
               d_out_reg    =  2'b10;
            end
            else
            begin
               nstate   =  3'b010;
               d_out_reg    =  2'b01;
            end
         end
         3'b110:
         begin
            if(d_in==1'b0)
            begin
               nstate   =  3'b111;
               d_out_reg    =  2'b00;
            end
            else
            begin
               nstate   =  3'b011;
               d_out_reg    =  2'b11;
            end
         end
         3'b111:
         begin
            if(d_in==1'b0)
            begin
               nstate   =  3'b011;
               d_out_reg    =  2'b00;
            end
            else
            begin
               nstate   =  3'b111;
               d_out_reg    =  2'b11;
            end
         end
 
      endcase
   end
 
 
 
   always @ (posedge clk,negedge rst)
   begin
//      $display("data in=%d state=%b%b%b data out=%b%b",d_in,reg_1,reg_2,reg_3,d_out_reg[1],d_out_reg[0]);
      if(rst==1'b0)
         cstate   <= 3'b000;
      else if(enable_i==1'b0)
         cstate   <= 3'b000;
      else
         cstate   <= nstate;
   end
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	sandunrath	`module encoder`
2			`(`
3			`clk,`
4			`rst,`
5			`enable_i,`
6			`d_in,`
7			`valid_o,`
8			`d_out`
9			`);`
10			`input clk;`
11			`input rst;`
12			`input enable_i;`
13			`input d_in;`
14			`output reg valid_o;`
15			`output [1:0] d_out;`
16
17			`reg [2:0] cstate;`
18			`reg [2:0] nstate;`
19
20			`reg [1:0] d_out_reg;`
21
22			`assign d_out = (enable_i==1'b1)?d_out_reg:2'b00;`
23
24
25			`always @(*) begin`
26			`valid_o = enable_i;`
27			`case (cstate)`
28			`3'b000:`
29			`begin`
30			`if(d_in==1'b0)`
31			`begin`
32			`nstate = 3'b000;`
33			`d_out_reg = 2'b00;`
34			`end`
35			`else`
36			`begin`
37			`nstate = 3'b100;`
38			`d_out_reg = 2'b11;`
39			`end`
40			`end`
41			`3'b001:`
42			`begin`
43			`if(d_in==1'b0)`
44			`begin`
45			`nstate = 3'b100;`
46			`d_out_reg = 2'b00;`
47			`end`
48			`else`
49			`begin`
50			`nstate = 3'b000;`
51			`d_out_reg = 2'b11;`
52			`end`
53			`end`
54			`3'b010:`
55			`begin`
56			`if(d_in==1'b0)`
57			`begin`
58			`nstate = 3'b101;`
59			`d_out_reg = 2'b10;`
60			`end`
61			`else`
62			`begin`
63			`nstate = 3'b001;`
64			`d_out_reg = 2'b01;`
65			`end`
66			`end`
67			`3'b011:`
68			`begin`
69			`if(d_in==1'b0)`
70			`begin`
71			`nstate = 3'b001;`
72			`d_out_reg = 2'b10;`
73			`end`
74			`else`
75			`begin`
76			`nstate = 3'b101;`
77			`d_out_reg = 2'b01;`
78			`end`
79			`end`
80			`3'b100:`
81			`begin`
82			`if(d_in==1'b0)`
83			`begin`
84			`nstate = 3'b010;`
85			`d_out_reg = 2'b10;`
86			`end`
87			`else`
88			`begin`
89			`nstate = 3'b110;`
90			`d_out_reg = 2'b01;`
91			`end`
92			`end`
93			`3'b101:`
94			`begin`
95			`if(d_in==1'b0)`
96			`begin`
97			`nstate = 3'b110;`
98			`d_out_reg = 2'b10;`
99			`end`
100			`else`
101			`begin`
102			`nstate = 3'b010;`
103			`d_out_reg = 2'b01;`
104			`end`
105			`end`
106			`3'b110:`
107			`begin`
108			`if(d_in==1'b0)`
109			`begin`
110			`nstate = 3'b111;`
111			`d_out_reg = 2'b00;`
112			`end`
113			`else`
114			`begin`
115			`nstate = 3'b011;`
116			`d_out_reg = 2'b11;`
117			`end`
118			`end`
119			`3'b111:`
120			`begin`
121			`if(d_in==1'b0)`
122			`begin`
123			`nstate = 3'b011;`
124			`d_out_reg = 2'b00;`
125			`end`
126			`else`
127			`begin`
128			`nstate = 3'b111;`
129			`d_out_reg = 2'b11;`
130			`end`
131			`end`
132
133			`endcase`
134			`end`
135
136
137
138			`always @ (posedge clk,negedge rst)`
139			`begin`
140			`// $display("data in=%d state=%b%b%b data out=%b%b",d_in,reg_1,reg_2,reg_3,d_out_reg[1],d_out_reg[0]);`
141			`if(rst==1'b0)`
142			`cstate <= 3'b000;`
143			`else if(enable_i==1'b0)`
144			`cstate <= 3'b000;`
145			`else`
146			`cstate <= nstate;`
147			`end`
148
149
150
151			`endmodule`

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[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [encoder.v] - Blame information for rev 2