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Subversion Repositories viterb_encoder_and_decoder

[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [mem_1x1024.v] - Blame information for rev 2

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module mem_disp
(
   clk,
   wr,
   addr,
   d_i,
   d_o
);
 
   input          clk;
   input          wr;
   input [9:0]    addr;
   input          d_i;
   output reg     d_o;
 
   reg            mem   [1023:0];
 
 
   always @ (posedge clk)
   begin
      if(wr)
         mem[addr]   <= d_i;
      d_o  <=  mem[addr];
  end
endmodule

Line No.	Rev	Author	Line
1	2	sandunrath	`module mem_disp`
2			`(`
3			`clk,`
4			`wr,`
5			`addr,`
6			`d_i,`
7			`d_o`
8			`);`
9
10			`input clk;`
11			`input wr;`
12			`input [9:0] addr;`
13			`input d_i;`
14			`output reg d_o;`
15
16			`reg mem [1023:0];`
17
18
19			`always @ (posedge clk)`
20			`begin`
21			`if(wr)`
22			`mem[addr] <= d_i;`
23			`d_o <= mem[addr];`
24			`end`
25			`endmodule`

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[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [mem_1x1024.v] - Blame information for rev 2