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[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [original/] [mem_8x1024_ori.v] - Blame information for rev 2

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module mem
(
   clk,
   wr,
   addr,
   d_i,
   d_o
);
 
   input          clk;
   input          wr;
   input [9:0]    addr;
   input [7:0]    d_i;
   output[7:0]    d_o;
 
   reg   [7:0]    mem   [1023:0];
 
   assign d_o  =  mem[addr];
 
   always @ (posedge clk)
   begin
      if(wr)
         mem[addr]   <= d_i;
 
   end
endmodule

Line No.	Rev	Author	Line
1	2	sandunrath	`module mem`
2			`(`
3			`clk,`
4			`wr,`
5			`addr,`
6			`d_i,`
7			`d_o`
8			`);`
9
10			`input clk;`
11			`input wr;`
12			`input [9:0] addr;`
13			`input [7:0] d_i;`
14			`output[7:0] d_o;`
15
16			`reg [7:0] mem [1023:0];`
17
18			`assign d_o = mem[addr];`
19
20			`always @ (posedge clk)`
21			`begin`
22			`if(wr)`
23			`mem[addr] <= d_i;`
24
25			`end`
26			`endmodule`

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[/] [viterb_encoder_and_decoder/] [trunk/] [rtl/] [original/] [mem_8x1024_ori.v] - Blame information for rev 2