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--!
--! Copyright (C) 2011 - 2012 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief  Component declarations for Viterbi decoder
--! @author Markus Fehrenz
--! @date   2011/04/07
--!
--!
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
 
package pkg_components is
 
        component branch_distance is
                generic(
                        EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0)
                );
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        s_axis_input_tvalid : in  std_logic;
                        s_axis_input_tdata  : in  t_input_block;
                        s_axis_input_tlast  : in  std_logic;
                        s_axis_input_tready : out std_logic;
 
                        m_axis_output_tvalid : out std_logic;
                        m_axis_output_tdata  : out std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
                        m_axis_output_tlast  : out std_logic;
                        m_axis_output_tready : in  std_logic
 
                );
        end component branch_distance;
 
        component acs is
                generic(
                        initialize_value : in signed(BW_MAX_PROBABILITY - 1 downto 0)
                );
                port(
                        clk                    : in std_logic;
                        rst                    : in std_logic;
 
                        s_axis_inbranch_tvalid     : in  std_logic;
                        s_axis_inbranch_tdata_low  : in  std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
                        s_axis_inbranch_tdata_high : in  std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
                        s_axis_inbranch_tlast      : in  std_logic;
                        s_axis_inbranch_tready     : out std_logic;
 
                        s_axis_inprev_tvalid     : in  std_logic;
                        s_axis_inprev_tdata_low  : in  std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
                        s_axis_inprev_tdata_high : in  std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
                        s_axis_inprev_tready     : out std_logic;
 
                        m_axis_outprob_tvalid  : out std_logic;
                        m_axis_outprob_tdata   : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
                        m_axis_outprob_tready  : in  std_logic;
 
                        m_axis_outdec_tvalid   : out std_logic;
                        m_axis_outdec_tdata    : out std_logic;
                        m_axis_outdec_tlast    : out std_logic;
                        m_axis_outdec_tready   : in  std_logic
                );
        end component acs;
 
        component ram_ctrl is
                port(
                        clk       : in std_logic;
                        rst       : in std_logic;
 
                        s_axis_input_tvalid : in  std_logic;
                        s_axis_input_tdata  : in  std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
                        s_axis_input_tlast  : in  std_logic;
                        s_axis_input_tready : out std_logic;
 
                        m_axis_output_tvalid       : out std_logic_vector(1 downto 0);
                        m_axis_output_tdata        : out t_ram_rd_data;
                        m_axis_output_tlast        : out std_logic_vector(1 downto 0);
                        m_axis_output_tready       : in  std_logic_vector(1 downto 0);
                        m_axis_output_window_tuser : out std_logic_vector(1 downto 0);
                        m_axis_output_last_tuser   : out std_logic_vector(1 downto 0);
 
                        s_axis_ctrl_tvalid : in  std_logic;
                        s_axis_ctrl_tdata  : in  std_logic_vector(31 downto 0);
                        s_axis_ctrl_tready : out std_logic
                );
        end component ram_ctrl;
 
        component generic_sp_ram is
                generic(
                        DISTR_RAM : boolean;
                        WORDS     : integer;
                        BITWIDTH  : integer
                );
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        wen : in std_logic;
                        en  : in std_logic;
 
                        a   : in std_logic_vector(BW_MAX_WINDOW_LENGTH - 1 downto 0);
                        d   : in  std_logic_vector(BITWIDTH - 1 downto 0 );
                        q   : out std_logic_vector(BITWIDTH - 1 downto 0)
                );
        end component generic_sp_ram;
 
        component trellis_traceback is
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        s_axis_input_tvalid       : in std_logic;
                        s_axis_input_tdata        : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
                        s_axis_input_tlast        : in std_logic;
                        s_axis_input_tready       : out std_logic;
                        s_axis_input_window_tuser : in std_logic;
                        s_axis_input_last_tuser   : in std_logic;
 
                        m_axis_output_tvalid     : out std_logic;
                        m_axis_output_tdata      : out std_logic;
                        m_axis_output_tlast      : out std_logic;
                        m_axis_output_last_tuser : out std_logic;
                        m_axis_output_tready     : in  std_logic
                );
        end component trellis_traceback;
 
        component reorder is
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        s_axis_input_tvalid     : in  std_logic;
                        s_axis_input_tdata      : in  std_logic;
                        s_axis_input_tlast      : in  std_logic;
                        s_axis_input_last_tuser : in  std_logic;
                        s_axis_input_tready     : out std_logic;
 
                        m_axis_output_tvalid     : out std_logic;
                        m_axis_output_tdata      : out std_logic;
                        m_axis_output_tlast      : out std_logic;
                        m_axis_output_last_tuser : out std_logic;
                        m_axis_output_tready     : in  std_logic
                );
        end component reorder;
 
        component recursion is
                port(
                        clk : in std_logic;
                        rst : in std_logic;
 
                        s_axis_input_tvalid     : in  std_logic;
                        s_axis_input_tdata      : in  std_logic;
                        s_axis_input_tlast      : in  std_logic;
                        s_axis_input_tready     : out std_logic;
 
                        m_axis_output_tvalid     : out std_logic;
                        m_axis_output_tdata      : out std_logic;
                        m_axis_output_tlast      : out std_logic;
                        m_axis_output_tready     : in  std_logic
                );
        end component recursion;
 
end package pkg_components;

Line No.	Rev	Author	Line
1	2	mfehrenz	`--!`
2			`--! Copyright (C) 2011 - 2012 Creonic GmbH`
3			`--!`
4			`--! This file is part of the Creonic Viterbi Decoder, which is distributed`
5			`--! under the terms of the GNU General Public License version 2.`
6			`--!`
7			`--! @file`
8			`--! @brief Component declarations for Viterbi decoder`
9			`--! @author Markus Fehrenz`
10			`--! @date 2011/04/07`
11			`--!`
12			`--!`
13
14			`library ieee;`
15			`use ieee.std_logic_1164.all;`
16			`use ieee.numeric_std.all;`
17
18			`library dec_viterbi;`
19			`use dec_viterbi.pkg_param.all;`
20			`use dec_viterbi.pkg_param_derived.all;`
21			`use dec_viterbi.pkg_types.all;`
22
23			`package pkg_components is`
24
25			`component branch_distance is`
26			`generic(`
27			`EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0)`
28			`);`
29			`port(`
30			`clk : in std_logic;`
31			`rst : in std_logic;`
32
33			`s_axis_input_tvalid : in std_logic;`
34			`s_axis_input_tdata : in t_input_block;`
35			`s_axis_input_tlast : in std_logic;`
36			`s_axis_input_tready : out std_logic;`
37
38			`m_axis_output_tvalid : out std_logic;`
39			`m_axis_output_tdata : out std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);`
40			`m_axis_output_tlast : out std_logic;`
41			`m_axis_output_tready : in std_logic`
42
43			`);`
44			`end component branch_distance;`
45
46			`component acs is`
47			`generic(`
48			`initialize_value : in signed(BW_MAX_PROBABILITY - 1 downto 0)`
49			`);`
50			`port(`
51			`clk : in std_logic;`
52			`rst : in std_logic;`
53
54			`s_axis_inbranch_tvalid : in std_logic;`
55			`s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);`
56			`s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);`
57			`s_axis_inbranch_tlast : in std_logic;`
58			`s_axis_inbranch_tready : out std_logic;`
59
60			`s_axis_inprev_tvalid : in std_logic;`
61			`s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);`
62			`s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);`
63			`s_axis_inprev_tready : out std_logic;`
64
65			`m_axis_outprob_tvalid : out std_logic;`
66			`m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);`
67			`m_axis_outprob_tready : in std_logic;`
68
69			`m_axis_outdec_tvalid : out std_logic;`
70			`m_axis_outdec_tdata : out std_logic;`
71			`m_axis_outdec_tlast : out std_logic;`
72			`m_axis_outdec_tready : in std_logic`
73			`);`
74			`end component acs;`
75
76			`component ram_ctrl is`
77			`port(`
78			`clk : in std_logic;`
79			`rst : in std_logic;`
80
81			`s_axis_input_tvalid : in std_logic;`
82			`s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);`
83			`s_axis_input_tlast : in std_logic;`
84			`s_axis_input_tready : out std_logic;`
85
86			`m_axis_output_tvalid : out std_logic_vector(1 downto 0);`
87			`m_axis_output_tdata : out t_ram_rd_data;`
88			`m_axis_output_tlast : out std_logic_vector(1 downto 0);`
89			`m_axis_output_tready : in std_logic_vector(1 downto 0);`
90			`m_axis_output_window_tuser : out std_logic_vector(1 downto 0);`
91			`m_axis_output_last_tuser : out std_logic_vector(1 downto 0);`
92
93			`s_axis_ctrl_tvalid : in std_logic;`
94			`s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);`
95			`s_axis_ctrl_tready : out std_logic`
96			`);`
97			`end component ram_ctrl;`
98
99			`component generic_sp_ram is`
100			`generic(`
101			`DISTR_RAM : boolean;`
102			`WORDS : integer;`
103			`BITWIDTH : integer`
104			`);`
105			`port(`
106			`clk : in std_logic;`
107			`rst : in std_logic;`
108
109			`wen : in std_logic;`
110			`en : in std_logic;`
111
112			`a : in std_logic_vector(BW_MAX_WINDOW_LENGTH - 1 downto 0);`
113			`d : in std_logic_vector(BITWIDTH - 1 downto 0 );`
114			`q : out std_logic_vector(BITWIDTH - 1 downto 0)`
115			`);`
116			`end component generic_sp_ram;`
117
118			`component trellis_traceback is`
119			`port(`
120			`clk : in std_logic;`
121			`rst : in std_logic;`
122
123			`s_axis_input_tvalid : in std_logic;`
124			`s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);`
125			`s_axis_input_tlast : in std_logic;`
126			`s_axis_input_tready : out std_logic;`
127			`s_axis_input_window_tuser : in std_logic;`
128			`s_axis_input_last_tuser : in std_logic;`
129
130			`m_axis_output_tvalid : out std_logic;`
131			`m_axis_output_tdata : out std_logic;`
132			`m_axis_output_tlast : out std_logic;`
133			`m_axis_output_last_tuser : out std_logic;`
134			`m_axis_output_tready : in std_logic`
135			`);`
136			`end component trellis_traceback;`
137
138			`component reorder is`
139			`port(`
140			`clk : in std_logic;`
141			`rst : in std_logic;`
142
143			`s_axis_input_tvalid : in std_logic;`
144			`s_axis_input_tdata : in std_logic;`
145			`s_axis_input_tlast : in std_logic;`
146			`s_axis_input_last_tuser : in std_logic;`
147			`s_axis_input_tready : out std_logic;`
148
149			`m_axis_output_tvalid : out std_logic;`
150			`m_axis_output_tdata : out std_logic;`
151			`m_axis_output_tlast : out std_logic;`
152			`m_axis_output_last_tuser : out std_logic;`
153			`m_axis_output_tready : in std_logic`
154			`);`
155			`end component reorder;`
156
157			`component recursion is`
158			`port(`
159			`clk : in std_logic;`
160			`rst : in std_logic;`
161
162			`s_axis_input_tvalid : in std_logic;`
163			`s_axis_input_tdata : in std_logic;`
164			`s_axis_input_tlast : in std_logic;`
165			`s_axis_input_tready : out std_logic;`
166
167			`m_axis_output_tvalid : out std_logic;`
168			`m_axis_output_tdata : out std_logic;`
169			`m_axis_output_tlast : out std_logic;`
170			`m_axis_output_tready : in std_logic`
171			`);`
172			`end component recursion;`
173
174			`end package pkg_components;`

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