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mfehrenz |
--!
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mfehrenz |
--! Copyright (C) 2011 - 2014 Creonic GmbH
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mfehrenz |
--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--!
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--! @file
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--! @brief Viterbi decoder RAM control
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--! @author Markus Fehrenz
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--! @date 2011/12/13
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--!
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--! @details Manage RAM behavior. Write and read data.
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--! The decisions are sent to the traceback units
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--! It is signaled if the data belongs to acquisition or window phase.
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--!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library dec_viterbi;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_types.all;
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use dec_viterbi.pkg_components.all;
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entity ram_ctrl is
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port(
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clk : in std_logic;
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rst : in std_logic;
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--
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-- Slave data signals, delivers the LLR parity values.
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--
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s_axis_input_tvalid : in std_logic;
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s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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s_axis_input_tlast : in std_logic;
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s_axis_input_tready : out std_logic;
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--
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-- Master data signals for traceback units, delivers the decision vectors.
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--
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m_axis_output_tvalid : out std_logic_vector(1 downto 0);
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m_axis_output_tdata : out t_ram_rd_data;
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m_axis_output_tlast : out std_logic_vector(1 downto 0);
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m_axis_output_tready : in std_logic_vector(1 downto 0);
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-- Signals the traceback unit when the decision bits do not belong to an acquisition.
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m_axis_output_window_tuser : out std_logic_vector(1 downto 0);
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-- Signals whether this is the last decision vector of the window.
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m_axis_output_last_tuser : out std_logic_vector(1 downto 0);
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--
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-- Slave configuration signals, delivering the configuration data.
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--
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s_axis_ctrl_tvalid : in std_logic;
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s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
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s_axis_ctrl_tready : out std_logic
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);
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end entity ram_ctrl;
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architecture rtl of ram_ctrl is
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------------------------
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-- Type definition
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------------------------
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--
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-- Record contains runtime configuration.
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-- The input configuration is stored in a register.
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-- It is received from a AXI4-Stream interface from the top entity.
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--
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type trec_runtime_param is record
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window_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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acquisition_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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end record trec_runtime_param;
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-- Types for finite state machines
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mfehrenz |
type t_write_ram_fsm is (CONFIGURE, START, RUN, WAIT_FOR_TRACEBACK, WAIT_FOR_LAST_TRACEBACK);
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type t_read_ram_fsm is (WAIT_FOR_WINDOW, TRACEBACK, WAIT_FOR_RAM, FINISH);
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type t_read_ram_fsm_array is array (0 to 1) of t_read_ram_fsm;
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-- RAM controling types
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type t_ram_data is array (3 downto 0) of std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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type t_ram_addr is array (3 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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type t_ram_rd_addr is array (1 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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type t_ram_ptr is array (1 downto 0) of unsigned(1 downto 0);
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type t_ram_ptr_int is array (1 downto 0) of integer range 3 downto 0;
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type t_ram_data_cnt is array (1 downto 0) of integer range 2 * MAX_WINDOW_LENGTH downto 0;
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------------------------
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-- Signal declaration
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------------------------
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signal ram_buffer : t_ram_rd_data;
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signal ram_buffer_full : std_logic_vector(1 downto 0);
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signal config : trec_runtime_param;
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signal write_ram_fsm : t_write_ram_fsm;
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signal read_ram_fsm : t_read_ram_fsm_array;
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signal wen_ram : std_logic_vector(3 downto 0);
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signal addr : t_ram_addr;
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signal q_reg : t_ram_data;
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-- ram addess, number and data pointer
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signal write_ram_ptr : unsigned(1 downto 0);
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signal read_ram_ptr : t_ram_ptr;
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signal read_ram_ptr_d : t_ram_ptr;
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signal write_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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signal read_addr_ptr : t_ram_rd_addr;
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-- internal signals of outputs
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signal m_axis_output_tvalid_int : std_logic_vector(1 downto 0);
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signal m_axis_output_tlast_int : std_logic_vector(1 downto 0);
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signal m_axis_output_window_tuser_int : std_logic_vector(1 downto 0);
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signal m_axis_output_last_tuser_int : std_logic_vector(1 downto 0);
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signal s_axis_input_tready_int : std_logic;
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signal s_axis_ctrl_tready_int : std_logic;
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mfehrenz |
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mfehrenz |
signal next_traceback : std_logic_vector(1 downto 0);
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signal write_window_complete : std_logic;
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signal write_last_window_complete : std_logic;
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signal last_of_block : std_logic;
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signal read_last_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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begin
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m_axis_output_tvalid <= m_axis_output_tvalid_int;
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m_axis_output_tlast <= m_axis_output_tlast_int;
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m_axis_output_window_tuser <= m_axis_output_window_tuser_int;
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m_axis_output_last_tuser <= m_axis_output_last_tuser_int;
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m_axis_output_tdata(0) <= q_reg(to_integer(read_ram_ptr_d(0))) when ram_buffer_full(0) = '0' else ram_buffer(0);
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m_axis_output_tdata(1) <= q_reg(to_integer(read_ram_ptr_d(1))) when ram_buffer_full(1) = '0' else ram_buffer(1);
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mfehrenz |
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--
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-- When the output port is not ready to read the output of the RAM immediately
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-- we have to remember the output value of the RAM in an extra register.
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-- When the output is ready to read, we first use the ouput of the register
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-- and only then the output of the RAM again.
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--
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pr_buf_ram_output: process(clk) is
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begin
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if rising_edge(clk) then
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if rst = '1' then
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ram_buffer <= (others => (others => '0'));
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ram_buffer_full <= (others => '0');
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else
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mfehrenz |
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mfehrenz |
for i in 0 to 1 loop
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if m_axis_output_tvalid_int(i) = '1' and m_axis_output_tready(i) = '0' and ram_buffer_full(i) = '0' then
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ram_buffer(i) <= q_reg(to_integer(read_ram_ptr_d(i)));
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ram_buffer_full(i) <= '1';
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end if;
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mfehrenz |
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mfehrenz |
if m_axis_output_tvalid_int(i) = '1' and m_axis_output_tready(i) = '1' and ram_buffer_full(i) = '1' then
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ram_buffer_full(i) <= '0';
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end if;
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end loop;
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mfehrenz |
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mfehrenz |
end if;
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end if;
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end process pr_buf_ram_output;
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mfehrenz |
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mfehrenz |
-----------------------------
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-- Manage writing from ACS --
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-----------------------------
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s_axis_input_tready_int <= '0' when (write_ram_fsm = CONFIGURE) or
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(write_ram_ptr = read_ram_ptr(0) and read_ram_fsm(0) /= WAIT_FOR_WINDOW) or
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(write_ram_ptr = read_ram_ptr(1) and read_ram_fsm(1) /= WAIT_FOR_WINDOW) or
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write_ram_fsm = WAIT_FOR_TRACEBACK or write_ram_fsm = WAIT_FOR_LAST_TRACEBACK else
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'1';
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s_axis_input_tready <= s_axis_input_tready_int;
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mfehrenz |
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mfehrenz |
s_axis_ctrl_tready_int <= '1' when (read_ram_fsm(0) = WAIT_FOR_WINDOW and read_ram_fsm(1) = WAIT_FOR_WINDOW and write_ram_fsm = CONFIGURE) else
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'0';
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s_axis_ctrl_tready <= s_axis_ctrl_tready_int;
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mfehrenz |
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mfehrenz |
-- Process for writing to the RAM
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pr_write_ram: process(clk) is
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variable v_window_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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variable v_acquisition_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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begin
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if rising_edge(clk) then
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if rst = '1' then
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write_ram_fsm <= CONFIGURE;
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write_addr_ptr <= (others => '0');
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write_ram_ptr <= (others => '0');
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wen_ram <= (others => '0');
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write_window_complete <= '0';
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write_last_window_complete <= '0';
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read_last_addr_ptr <= (others => '0');
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mfehrenz |
else
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mfehrenz |
case write_ram_fsm is
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mfehrenz |
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--
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-- It is necessary to configure the decoder before each block
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--
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when CONFIGURE =>
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write_window_complete <= '0';
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write_last_window_complete <= '0';
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if s_axis_ctrl_tvalid = '1' and s_axis_ctrl_tready_int = '1' then
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v_window_length := unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 + 16 downto 16));
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v_acquisition_length := unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 downto 0));
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write_addr_ptr <= v_window_length - v_acquisition_length;
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config.window_length <= v_window_length;
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config.acquisition_length <= v_acquisition_length;
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write_ram_fsm <= START;
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wen_ram(to_integer(write_ram_ptr)) <= '1';
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mfehrenz |
end if;
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6 |
mfehrenz |
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2 |
mfehrenz |
--
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mfehrenz |
-- After the decoder is configured, the decoder is waiting for a new block.
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-- When the AXIS handshake is there the packet transmission begins.
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-- The first write is a special case, since writing data starts at the acquisition length.
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-- There is no complete window available afterwards.
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mfehrenz |
--
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when START =>
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if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
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6 |
mfehrenz |
if write_addr_ptr = config.window_length - 1 then
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2 |
mfehrenz |
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mfehrenz |
-- When we switch to the next RAM, we reset the write addr.
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write_addr_ptr <= (others => '0');
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-- Switch to the next RAM.
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write_ram_ptr <= write_ram_ptr + 1;
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wen_ram(to_integer(write_ram_ptr)) <= '0';
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wen_ram(to_integer(write_ram_ptr + 1)) <= '1';
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write_ram_fsm <= RUN;
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mfehrenz |
else
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mfehrenz |
write_addr_ptr <= write_addr_ptr + 1;
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mfehrenz |
end if;
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end if;
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6 |
mfehrenz |
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2 |
mfehrenz |
--
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6 |
mfehrenz |
-- The decoder is receiving data from the ACS.
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2 |
mfehrenz |
--
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mfehrenz |
when RUN =>
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write_window_complete <= '0';
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write_last_window_complete <= '0';
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2 |
mfehrenz |
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6 |
mfehrenz |
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
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write_addr_ptr <= write_addr_ptr + 1;
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2 |
mfehrenz |
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6 |
mfehrenz |
if write_addr_ptr = config.window_length - 1 then
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-- When we switch to the next RAM, we reset the write addr.
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write_addr_ptr <= (others => '0');
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-- Switch to the next RAM.
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write_ram_ptr <= write_ram_ptr + 1;
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wen_ram(to_integer(write_ram_ptr)) <= '0';
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wen_ram(to_integer(write_ram_ptr + 1)) <= '1';
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-- Indicate, that a complete window is within the RAM and traceback may start.
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write_window_complete <= '1';
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if read_ram_fsm(0) /= WAIT_FOR_WINDOW and read_ram_fsm(1) /= WAIT_FOR_WINDOW then
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write_ram_fsm <= WAIT_FOR_TRACEBACK;
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2 |
mfehrenz |
end if;
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else
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write_addr_ptr <= write_addr_ptr + 1;
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end if;
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6 |
mfehrenz |
if s_axis_input_tlast = '1' then
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write_ram_fsm <= CONFIGURE;
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wen_ram <= (others => '0');
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2 |
mfehrenz |
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6 |
mfehrenz |
write_last_window_complete <= '1';
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if (read_ram_fsm(0) /= WAIT_FOR_WINDOW and read_ram_fsm(1) /= WAIT_FOR_WINDOW) or write_window_complete = '1' then
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write_ram_fsm <= WAIT_FOR_LAST_TRACEBACK;
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2 |
mfehrenz |
end if;
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6 |
mfehrenz |
read_last_addr_ptr <= write_addr_ptr;
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2 |
mfehrenz |
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6 |
mfehrenz |
write_addr_ptr <= (others => '0');
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write_ram_ptr <= write_ram_ptr + 1;
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end if;
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end if;
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2 |
mfehrenz |
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6 |
mfehrenz |
when WAIT_FOR_TRACEBACK =>
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if read_ram_fsm(0) = WAIT_FOR_WINDOW or read_ram_fsm(1) = WAIT_FOR_WINDOW then
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write_ram_fsm <= RUN;
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write_window_complete <= '0';
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2 |
mfehrenz |
end if;
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6 |
mfehrenz |
when WAIT_FOR_LAST_TRACEBACK =>
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if read_ram_fsm(0) = WAIT_FOR_WINDOW or read_ram_fsm(1) = WAIT_FOR_WINDOW then
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write_ram_fsm <= CONFIGURE;
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write_last_window_complete <= '0';
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end if;
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306 |
2 |
mfehrenz |
|
307 |
6 |
mfehrenz |
end case;
|
308 |
|
|
end if;
|
309 |
|
|
end if;
|
310 |
|
|
end process pr_write_ram;
|
311 |
2 |
mfehrenz |
|
312 |
|
|
|
313 |
6 |
mfehrenz |
-------------------------------------------
|
314 |
|
|
-- Manage reading from RAM for traceback --
|
315 |
|
|
-------------------------------------------
|
316 |
2 |
mfehrenz |
|
317 |
6 |
mfehrenz |
gen_read_ram: for i in 0 to 1 generate
|
318 |
|
|
pr_read_ram: process(clk) is
|
319 |
|
|
begin
|
320 |
|
|
if rising_edge(clk) then
|
321 |
|
|
if rst = '1' then
|
322 |
|
|
read_addr_ptr(i) <= (others => '0');
|
323 |
|
|
read_ram_fsm(i) <= WAIT_FOR_WINDOW;
|
324 |
|
|
m_axis_output_tvalid_int(i) <= '0';
|
325 |
|
|
m_axis_output_tlast_int(i) <= '0';
|
326 |
|
|
m_axis_output_window_tuser_int(i) <= '0';
|
327 |
|
|
m_axis_output_last_tuser_int(i) <= '0';
|
328 |
|
|
read_ram_ptr(i) <= (others => '0');
|
329 |
|
|
read_ram_ptr_d(i) <= (others => '0');
|
330 |
|
|
else
|
331 |
|
|
|
332 |
|
|
read_ram_ptr_d(i) <= read_ram_ptr(i);
|
333 |
|
|
case read_ram_fsm(i) is
|
334 |
|
|
|
335 |
|
|
-- Wait for the next window to be ready within the RAM.
|
336 |
|
|
when WAIT_FOR_WINDOW =>
|
337 |
|
|
read_addr_ptr(i) <= config.window_length - 1;
|
338 |
|
|
m_axis_output_tlast_int(i) <= '0';
|
339 |
|
|
m_axis_output_tvalid_int(i) <= '0';
|
340 |
|
|
m_axis_output_last_tuser_int(i) <= '0';
|
341 |
|
|
m_axis_output_window_tuser_int(i) <= '0';
|
342 |
|
|
read_ram_ptr(i) <= write_ram_ptr;
|
343 |
|
|
|
344 |
|
|
-- We always start from the RAM, which was written last.
|
345 |
|
|
if write_window_complete = '1' and next_traceback(i) = '1' then
|
346 |
|
|
read_ram_ptr(i) <= write_ram_ptr - 1;
|
347 |
|
|
read_addr_ptr(i) <= read_addr_ptr(i) - 1;
|
348 |
|
|
read_ram_fsm(i) <= TRACEBACK;
|
349 |
|
|
m_axis_output_tvalid_int(i) <= '1';
|
350 |
2 |
mfehrenz |
end if;
|
351 |
6 |
mfehrenz |
if write_last_window_complete = '1' and next_traceback(i) = '1' then
|
352 |
|
|
read_ram_ptr(i) <= write_ram_ptr - 1;
|
353 |
|
|
read_addr_ptr(i) <= read_last_addr_ptr;
|
354 |
|
|
read_ram_fsm(i) <= TRACEBACK;
|
355 |
|
|
m_axis_output_window_tuser_int(i) <= '1';
|
356 |
|
|
end if;
|
357 |
2 |
mfehrenz |
|
358 |
6 |
mfehrenz |
-- Perform the Traceback on the RAM data of the first RAM we need for acquisition and traceback.
|
359 |
|
|
when TRACEBACK =>
|
360 |
|
|
m_axis_output_tlast_int(i) <= '0';
|
361 |
|
|
m_axis_output_last_tuser_int(i) <= '0';
|
362 |
|
|
m_axis_output_tvalid_int(i) <= '1';
|
363 |
|
|
|
364 |
|
|
if m_axis_output_tready(i) = '1' then
|
365 |
|
|
if read_addr_ptr(i) = 0 then
|
366 |
|
|
if read_ram_fsm(1 - i) = TRACEBACK and read_ram_ptr(1 - i) = read_ram_ptr(i) - 1 then
|
367 |
|
|
read_ram_fsm(i) <= WAIT_FOR_RAM;
|
368 |
|
|
else
|
369 |
|
|
read_addr_ptr(i) <= config.window_length - 1;
|
370 |
|
|
read_ram_ptr(i) <= read_ram_ptr(i) - 1;
|
371 |
|
|
read_ram_fsm(i) <= FINISH;
|
372 |
|
|
end if;
|
373 |
|
|
else
|
374 |
|
|
read_addr_ptr(i) <= read_addr_ptr(i) - 1;
|
375 |
|
|
end if;
|
376 |
|
|
|
377 |
|
|
-- Signal the traceback unit, acquisition is over.
|
378 |
|
|
if read_addr_ptr(i) = config.window_length - config.acquisition_length - 1 then
|
379 |
|
|
m_axis_output_window_tuser_int(i) <= '1';
|
380 |
|
|
end if;
|
381 |
2 |
mfehrenz |
end if;
|
382 |
|
|
|
383 |
6 |
mfehrenz |
when WAIT_FOR_RAM =>
|
384 |
|
|
m_axis_output_tvalid_int(i) <= '0';
|
385 |
|
|
if read_ram_fsm(1 - i) /= TRACEBACK or read_ram_ptr(1 - i) /= read_ram_ptr(i) - 1 then
|
386 |
|
|
read_addr_ptr(i) <= config.window_length - 1;
|
387 |
|
|
read_ram_ptr(i) <= read_ram_ptr(i) - 1;
|
388 |
|
|
read_ram_fsm(i) <= FINISH;
|
389 |
2 |
mfehrenz |
end if;
|
390 |
|
|
|
391 |
6 |
mfehrenz |
-- Get the remaining values from the second RAM we need for traceback (no acquisition values in this RAM)
|
392 |
|
|
when FINISH =>
|
393 |
|
|
if m_axis_output_tvalid_int(i) <= '0' then
|
394 |
|
|
m_axis_output_tvalid_int(i) <= '1';
|
395 |
|
|
read_addr_ptr(i) <= read_addr_ptr(i) - 1;
|
396 |
2 |
mfehrenz |
end if;
|
397 |
6 |
mfehrenz |
if m_axis_output_tready(i) = '1' then
|
398 |
2 |
mfehrenz |
|
399 |
6 |
mfehrenz |
if read_addr_ptr(i) = config.window_length - config.acquisition_length then
|
400 |
|
|
m_axis_output_last_tuser_int(i) <= '1';
|
401 |
|
|
read_addr_ptr(i) <= config.window_length - 1;
|
402 |
|
|
read_ram_fsm(i) <= WAIT_FOR_WINDOW;
|
403 |
|
|
|
404 |
|
|
-- Check if the other read process finished processing.
|
405 |
|
|
if read_ram_fsm((i+1) mod 2) = WAIT_FOR_WINDOW and last_of_block = '1' then
|
406 |
|
|
m_axis_output_tlast_int(i) <= '1';
|
407 |
|
|
end if;
|
408 |
|
|
|
409 |
|
|
else
|
410 |
|
|
read_addr_ptr(i) <= read_addr_ptr(i) - 1;
|
411 |
|
|
end if;
|
412 |
2 |
mfehrenz |
end if;
|
413 |
6 |
mfehrenz |
end case;
|
414 |
|
|
end if;
|
415 |
|
|
end if;
|
416 |
|
|
end process pr_read_ram;
|
417 |
|
|
end generate gen_read_ram;
|
418 |
2 |
mfehrenz |
|
419 |
6 |
mfehrenz |
-- This process decides which traceback unit is the next one to use.
|
420 |
|
|
pr_next_traceback: process(clk) is
|
421 |
|
|
begin
|
422 |
|
|
if rising_edge(clk) then
|
423 |
|
|
if rst = '1' then
|
424 |
|
|
next_traceback <= "01";
|
425 |
|
|
last_of_block <= '0';
|
426 |
|
|
else
|
427 |
|
|
if write_window_complete = '1' then
|
428 |
|
|
if next_traceback(0) = '1' then
|
429 |
|
|
next_traceback(0) <= '0';
|
430 |
|
|
next_traceback(1) <= '1';
|
431 |
|
|
else
|
432 |
|
|
next_traceback(0) <= '1';
|
433 |
|
|
next_traceback(1) <= '0';
|
434 |
2 |
mfehrenz |
end if;
|
435 |
6 |
mfehrenz |
end if;
|
436 |
|
|
|
437 |
|
|
if s_axis_input_tlast = '1' then
|
438 |
|
|
last_of_block <= '1';
|
439 |
|
|
end if;
|
440 |
|
|
|
441 |
2 |
mfehrenz |
end if;
|
442 |
|
|
end if;
|
443 |
6 |
mfehrenz |
end process pr_next_traceback;
|
444 |
2 |
mfehrenz |
|
445 |
|
|
------------------------------
|
446 |
|
|
--- Portmapping components ---
|
447 |
|
|
------------------------------
|
448 |
|
|
|
449 |
|
|
gen_generic_sp_ram : for i in 0 to 3 generate
|
450 |
|
|
begin
|
451 |
6 |
mfehrenz |
|
452 |
|
|
addr(i) <= write_addr_ptr when (write_ram_fsm = RUN or write_ram_fsm = START) and to_integer(write_ram_ptr) = i else
|
453 |
|
|
read_addr_ptr(0) when (to_integer(read_ram_ptr(0)) = i and (read_ram_fsm(0) = TRACEBACK or read_ram_fsm(0) = WAIT_FOR_RAM or read_ram_fsm(0) = FINISH)) or
|
454 |
|
|
(next_traceback(0) = '1' and write_window_complete = '1' and to_integer(read_ram_ptr(0)) = i) else
|
455 |
|
|
read_addr_ptr(1);
|
456 |
|
|
|
457 |
|
|
inst_generic_sp_ram : generic_sp_ram
|
458 |
2 |
mfehrenz |
generic map(
|
459 |
|
|
DISTR_RAM => DISTRIBUTED_RAM,
|
460 |
|
|
WORDS => MAX_WINDOW_LENGTH,
|
461 |
|
|
BITWIDTH => NUMBER_TRELLIS_STATES
|
462 |
|
|
)
|
463 |
|
|
port map(
|
464 |
|
|
clk => clk,
|
465 |
|
|
rst => rst,
|
466 |
|
|
wen => wen_ram(i),
|
467 |
6 |
mfehrenz |
en => '1',
|
468 |
2 |
mfehrenz |
a => std_logic_vector(addr(i)),
|
469 |
6 |
mfehrenz |
d => s_axis_input_tdata,
|
470 |
2 |
mfehrenz |
q => q_reg(i)
|
471 |
|
|
);
|
472 |
|
|
end generate gen_generic_sp_ram;
|
473 |
|
|
|
474 |
|
|
end architecture rtl;
|