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mfehrenz |
--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--!
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--! @file
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--! @brief Viterbi decoder RAM control
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--! @author Markus Fehrenz
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--! @date 2011/12/13
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--!
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--! @details Manage RAM behavior. Write and read data.
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--! The decisions are sent to the traceback units
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--! It is signaled if the data belongs to acquisition or window phase.
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--!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library dec_viterbi;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_types.all;
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use dec_viterbi.pkg_components.all;
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entity ram_ctrl is
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port(
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clk : in std_logic;
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rst : in std_logic;
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--
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-- Slave data signals, delivers the LLR parity values.
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--
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s_axis_input_tvalid : in std_logic;
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s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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s_axis_input_tlast : in std_logic;
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s_axis_input_tready : out std_logic;
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--
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-- Master data signals for traceback units, delivers the decision vectors.
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--
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m_axis_output_tvalid : out std_logic_vector(1 downto 0);
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m_axis_output_tdata : out t_ram_rd_data;
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m_axis_output_tlast : out std_logic_vector(1 downto 0);
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m_axis_output_tready : in std_logic_vector(1 downto 0);
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-- Signals the traceback unit when the decision bits do not belong to an acquisition.
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m_axis_output_window_tuser : out std_logic_vector(1 downto 0);
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-- Signals whether this is the last decision vector of the window.
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m_axis_output_last_tuser : out std_logic_vector(1 downto 0);
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--
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-- Slave configuration signals, delivering the configuration data.
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--
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s_axis_ctrl_tvalid : in std_logic;
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s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
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s_axis_ctrl_tready : out std_logic
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);
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end entity ram_ctrl;
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architecture rtl of ram_ctrl is
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------------------------
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-- Type definition
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------------------------
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--
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-- Record contains runtime configuration.
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-- The input configuration is stored in a register.
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-- It is received from a AXI4-Stream interface from the top entity.
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--
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-- We just receive window_length and acquisition_length from the outside. All
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-- other values are computed internally in order to impreove timing of the core:
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-- m denotes minus,
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-- p denotes plus.
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--
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type trec_runtime_param is record
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window_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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acquisition_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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window_p_acquisition : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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window_p_acquisition_m1 : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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window_p_acquisition_m2 : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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window_p_acquisition_m3 : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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window_m1 : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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end record trec_runtime_param;
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-- Types for finite state machines
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type t_ram_ctrl is (CONFIGURE, START, BEGINNING, RUNNING, ENDING);
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-- RAM controling types
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type t_ram_data is array (3 downto 0) of std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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type t_ram_addr is array (3 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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type t_ram_rd_addr is array (1 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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type t_ram_ptr is array (1 downto 0) of unsigned(1 downto 0);
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type t_ram_ptr_int is array (1 downto 0) of integer range 3 downto 0;
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type t_ram_data_cnt is array (1 downto 0) of integer range 2 * MAX_WINDOW_LENGTH downto 0;
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------------------------
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-- Signal declaration
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------------------------
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signal config : trec_runtime_param;
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signal ram_ctrl_fsm : t_ram_ctrl;
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signal en_ram, wen_ram : std_logic_vector(3 downto 0);
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signal addr : t_ram_addr;
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signal d : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal q : t_ram_rd_data;
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signal q_reg : t_ram_data;
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-- ram addess, number and data pointer
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signal write_ram_ptr : unsigned(1 downto 0);
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signal read_ram_ptr, read_ram_data_ptr : t_ram_ptr;
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signal read_ram_data_ptr_d1 : t_ram_ptr;
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signal write_addr_ptr, read_addr_ptr, last_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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-- control flags
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signal switch_ram, switch_state, ram_writing : boolean;
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-- internal signals of outputs
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signal m_axis_output_tvalid_int : std_logic_vector(1 downto 0);
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signal m_axis_output_last_tuser_int : std_logic_vector(1 downto 0);
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signal s_axis_input_tready_int : std_logic;
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-- delay signals of inputs
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signal m_axis_output_tvalid_d1, m_axis_output_tvalid_d2 : std_logic_vector(1 downto 0);
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signal next_traceback, not_next_traceback : integer range 1 downto 0;
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signal data_cnt : t_ram_data_cnt;
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begin
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s_axis_input_tready <= '1' when (m_axis_output_tready = "11" or m_axis_output_tvalid_int(0) = '0'
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or m_axis_output_tvalid_int(1) = '0')
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and ram_ctrl_fsm /= CONFIGURE and ram_ctrl_fsm /= ENDING else
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'0';
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s_axis_input_tready_int <= '1' when (m_axis_output_tready = "11" or m_axis_output_tvalid_int(0) = '0'
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or m_axis_output_tvalid_int(1) = '0')
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and ram_ctrl_fsm /= CONFIGURE and ram_ctrl_fsm /= ENDING else
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'0';
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m_axis_output_last_tuser <= m_axis_output_last_tuser_int;
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m_axis_output_tvalid <= m_axis_output_tvalid_int;
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m_axis_output_tdata <= q;
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--
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-- Statemachine handles configuration, write/read to/from ram
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-- and forwarding decision vectors to corresponding traceback units
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--
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pr_ctrl_ram : process(clk, write_ram_ptr, read_ram_ptr) is
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variable v_write_ram_ptr : integer range 3 downto 0;
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variable v_read_ram_ptr : t_ram_ptr_int;
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begin
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v_write_ram_ptr := to_integer(write_ram_ptr);
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v_read_ram_ptr(0) := to_integer(read_ram_ptr(0));
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v_read_ram_ptr(1) := to_integer(read_ram_ptr(1));
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if rising_edge(clk) then
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if rst = '1' then
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ram_ctrl_fsm <= CONFIGURE;
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config.window_length <= (others => '0');
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config.acquisition_length <= (others => '0');
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en_ram <= (others => '1');
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wen_ram <= (others => '0');
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addr <= (others => (others => '0'));
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write_ram_ptr <= to_unsigned(0, 2);
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write_addr_ptr <= (others => '0');
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last_addr_ptr <= (others => '0');
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read_ram_ptr <= (to_unsigned(2, 2), to_unsigned(3, 2));
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read_ram_data_ptr <= (to_unsigned(2, 2), to_unsigned(3, 2));
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read_ram_data_ptr_d1 <= (to_unsigned(2, 2), to_unsigned(3, 2));
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read_addr_ptr <= (others => '0');
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next_traceback <= 0;
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not_next_traceback <= 1;
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switch_ram <= false;
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switch_state <= false;
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ram_writing <= true;
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m_axis_output_last_tuser_int <= (others => '0');
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m_axis_output_window_tuser <= (others => '0');
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m_axis_output_tvalid_int <= (others => '0');
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m_axis_output_tvalid_d1 <= (others => '0');
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m_axis_output_tvalid_d2 <= (others => '0');
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m_axis_output_tlast <= (others => '0');
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s_axis_ctrl_tready <= '1';
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else
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addr(v_write_ram_ptr) <= write_addr_ptr;
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addr(v_read_ram_ptr(0)) <= read_addr_ptr;
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addr(v_read_ram_ptr(1)) <= read_addr_ptr;
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d <= s_axis_input_tdata;
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q(0) <= q_reg(to_integer(read_ram_data_ptr(0)));
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q(1) <= q_reg(to_integer(read_ram_data_ptr(1)));
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case ram_ctrl_fsm is
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--
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-- It is necessary to configure the decoder before each block
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-- The decoder is always ready to receive on the ctrl channel, when it is in this state
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--
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when CONFIGURE =>
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if s_axis_ctrl_tvalid = '1' then
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config.window_length <= unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 + 16 downto 16));
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config.acquisition_length <= unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 downto 0));
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ram_ctrl_fsm <= START;
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wen_ram(v_write_ram_ptr) <= '1';
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s_axis_ctrl_tready <= '0';
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end if;
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--
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-- After the decoder is configured, the decoder is waiting for a new block
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-- When the AXIS handshake is there the packettransmission begins
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--
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when START =>
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if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
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ram_ctrl_fsm <= BEGINNING;
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write_addr_ptr <= write_addr_ptr + 1;
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read_ram_ptr(next_traceback) <= write_ram_ptr - 1;
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read_ram_ptr(not_next_traceback) <= write_ram_ptr - 2;
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else
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write_addr_ptr <= config.window_length - config.acquisition_length;
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config.window_p_acquisition <= config.window_length + config.acquisition_length;
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config.window_p_acquisition_m1 <= config.window_length + config.acquisition_length - 1;
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config.window_p_acquisition_m2 <= config.window_length + config.acquisition_length - 2;
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config.window_p_acquisition_m3 <= config.window_length + config.acquisition_length - 3;
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config.window_m1 <= config.window_length - 1;
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end if;
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--
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-- The first arriving data have to be stored on special locations to guarantee
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-- a non malicious behavior of the traceback units.
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--
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when BEGINNING =>
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if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
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if switch_ram then
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ram_ctrl_fsm <= RUNNING;
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wen_ram(to_integer(unsigned(write_ram_ptr - 1))) <= '0';
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wen_ram(v_write_ram_ptr) <= '1';
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write_addr_ptr <= write_addr_ptr + 1;
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read_addr_ptr <= read_addr_ptr - 1;
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switch_ram <= false;
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else
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if write_addr_ptr = config.window_m1 then
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write_addr_ptr <= to_unsigned(0, BW_MAX_WINDOW_LENGTH);
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read_addr_ptr <= config.window_m1;
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write_ram_ptr <= write_ram_ptr + 1;
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switch_ram <= true;
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else
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write_addr_ptr <= write_addr_ptr + 1;
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end if;
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end if;
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end if;
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--
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-- The running state handles the most decoding
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-- It handels the writing of forward to ram and reading the decision vecotors
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-- the decision vecotrs are forwarded to the traceback units.
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--
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when RUNNING =>
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if (s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' and ram_writing) or
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((m_axis_output_tready(0) = '1' and m_axis_output_tready(1) = '1') and not(ram_writing)) then
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read_ram_data_ptr_d1 <= read_ram_ptr;
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read_ram_data_ptr <= read_ram_data_ptr_d1;
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m_axis_output_tvalid_int <= m_axis_output_tvalid_d1;
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m_axis_output_tvalid_d1 <= m_axis_output_tvalid_d2;
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if switch_ram then
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if ram_writing then
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wen_ram(to_integer(unsigned(write_ram_ptr - 1))) <= '0';
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wen_ram(v_write_ram_ptr) <= '1';
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next_traceback <= not_next_traceback;
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not_next_traceback <= next_traceback;
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else
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ram_ctrl_fsm <= ENDING;
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ram_writing <= true;
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wen_ram(to_integer(unsigned(write_ram_ptr - 1))) <= '0';
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end if;
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switch_ram <= false;
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else
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if write_addr_ptr = config.window_m1 then
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write_ram_ptr <= write_ram_ptr + 1;
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read_ram_ptr(next_traceback) <= write_ram_ptr;
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read_ram_ptr(not_next_traceback) <= write_ram_ptr - 2;
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switch_ram <= true;
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data_cnt(next_traceback) <= 0;
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end if;
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end if;
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-- Store last RAM address and stop writing after last bit of a block arrives
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if s_axis_input_tlast = '1' then
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ram_writing <= false;
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last_addr_ptr <= write_addr_ptr;
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-- wen_ram(v_write_ram_ptr) <= '0';
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end if;
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-- Handle RAM addess point increase and reset
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if write_addr_ptr = config.window_m1 then
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write_addr_ptr <= to_unsigned(0, BW_MAX_WINDOW_LENGTH);
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read_addr_ptr <= config.window_m1;
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else
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write_addr_ptr <= write_addr_ptr + 1;
|
321 |
|
|
read_addr_ptr <= read_addr_ptr - 1;
|
322 |
|
|
end if;
|
323 |
|
|
|
324 |
|
|
-- Handle side channel information for traceback units.
|
325 |
|
|
for i in 1 downto 0 loop
|
326 |
|
|
if m_axis_output_tvalid_d1(i) = '1' then
|
327 |
|
|
data_cnt(i) <= data_cnt(i) + 1;
|
328 |
|
|
end if;
|
329 |
|
|
|
330 |
|
|
-- Signals the valid signal
|
331 |
|
|
if data_cnt(i) = config.window_p_acquisition_m2 then
|
332 |
|
|
m_axis_output_tvalid_d2(i) <= '0';
|
333 |
|
|
end if;
|
334 |
|
|
if switch_ram and ram_writing then
|
335 |
|
|
m_axis_output_tvalid_d2(next_traceback) <= '1';
|
336 |
|
|
end if;
|
337 |
|
|
|
338 |
|
|
-- Signals the end of the current window
|
339 |
|
|
if m_axis_output_last_tuser_int(i) = '1' then
|
340 |
|
|
m_axis_output_last_tuser_int(i) <= '0';
|
341 |
|
|
end if;
|
342 |
|
|
if data_cnt(i) = config.window_p_acquisition_m1 then
|
343 |
|
|
m_axis_output_last_tuser_int(i) <= '1';
|
344 |
|
|
end if;
|
345 |
|
|
|
346 |
|
|
-- Signals, whether there is acquisition or window
|
347 |
|
|
if data_cnt(i) = config.window_p_acquisition then
|
348 |
|
|
m_axis_output_window_tuser(i) <= '0';
|
349 |
|
|
end if;
|
350 |
|
|
if data_cnt(i) = config.acquisition_length then
|
351 |
|
|
m_axis_output_window_tuser(i) <= '1';
|
352 |
|
|
end if;
|
353 |
|
|
end loop;
|
354 |
|
|
end if;
|
355 |
|
|
|
356 |
|
|
--
|
357 |
|
|
-- Handle last traceback with no acquisition
|
358 |
|
|
-- Maybe the resulting window is longer than others
|
359 |
|
|
--
|
360 |
|
|
when ENDING =>
|
361 |
|
|
if m_axis_output_tready(0) = '1' and m_axis_output_tready(1) = '1' then
|
362 |
|
|
|
363 |
|
|
read_ram_data_ptr_d1 <= read_ram_ptr;
|
364 |
|
|
read_ram_data_ptr <= read_ram_data_ptr_d1;
|
365 |
|
|
m_axis_output_tvalid_int <= m_axis_output_tvalid_d1;
|
366 |
|
|
|
367 |
|
|
for i in 1 downto 0 loop
|
368 |
|
|
if m_axis_output_tvalid_int(i) = '1' then
|
369 |
|
|
data_cnt(i) <= data_cnt(i) + 1;
|
370 |
|
|
end if;
|
371 |
|
|
end loop;
|
372 |
|
|
|
373 |
|
|
if data_cnt(not_next_traceback) = config.window_p_acquisition_m3 then
|
374 |
|
|
read_addr_ptr <= last_addr_ptr;
|
375 |
|
|
elsif read_addr_ptr = 0 then
|
376 |
|
|
read_ram_ptr(0) <= read_ram_ptr(0) - 1;
|
377 |
|
|
read_ram_ptr(1) <= read_ram_ptr(1) - 1;
|
378 |
|
|
read_addr_ptr <= config.window_m1;
|
379 |
|
|
else
|
380 |
|
|
read_addr_ptr <= read_addr_ptr - 1;
|
381 |
|
|
end if;
|
382 |
|
|
|
383 |
|
|
if data_cnt(not_next_traceback) = config.window_p_acquisition_m1 then
|
384 |
|
|
m_axis_output_last_tuser_int(not_next_traceback) <= '1';
|
385 |
|
|
m_axis_output_tvalid_d1(next_traceback) <= '1';
|
386 |
|
|
m_axis_output_tvalid_d1(not_next_traceback) <= '0';
|
387 |
|
|
end if;
|
388 |
|
|
|
389 |
|
|
if data_cnt(not_next_traceback) = config.window_p_acquisition then
|
390 |
|
|
m_axis_output_window_tuser(not_next_traceback) <= '0';
|
391 |
|
|
m_axis_output_window_tuser(next_traceback) <= '1';
|
392 |
|
|
end if;
|
393 |
|
|
|
394 |
|
|
if data_cnt(not_next_traceback) = config.acquisition_length then
|
395 |
|
|
m_axis_output_window_tuser(not_next_traceback) <= '1';
|
396 |
|
|
end if;
|
397 |
|
|
|
398 |
|
|
if m_axis_output_last_tuser_int(not_next_traceback) = '1' then
|
399 |
|
|
m_axis_output_last_tuser_int(not_next_traceback) <= '0';
|
400 |
|
|
end if;
|
401 |
|
|
|
402 |
|
|
if data_cnt(next_traceback) = last_addr_ptr + config.acquisition_length - 1 then
|
403 |
|
|
m_axis_output_tvalid_d1(next_traceback) <= '0';
|
404 |
|
|
m_axis_output_last_tuser_int(next_traceback) <= '1';
|
405 |
|
|
m_axis_output_tlast(next_traceback) <= '1';
|
406 |
|
|
switch_state <= true;
|
407 |
|
|
end if;
|
408 |
|
|
|
409 |
|
|
-- block is finished and the decoder is ready for a new configuration and block
|
410 |
|
|
if switch_state then
|
411 |
|
|
switch_state <= false;
|
412 |
|
|
m_axis_output_last_tuser_int <= "00";
|
413 |
|
|
m_axis_output_window_tuser <= "00";
|
414 |
|
|
m_axis_output_tlast <= "00";
|
415 |
|
|
ram_ctrl_fsm <= CONFIGURE;
|
416 |
|
|
s_axis_ctrl_tready <= '1';
|
417 |
|
|
data_cnt(0) <= 0;
|
418 |
|
|
data_cnt(1) <= 0;
|
419 |
|
|
m_axis_output_tvalid_int <= (others => '0');
|
420 |
|
|
m_axis_output_tvalid_d1 <= (others => '0');
|
421 |
|
|
m_axis_output_tvalid_d2 <= (others => '0');
|
422 |
|
|
end if;
|
423 |
|
|
end if;
|
424 |
|
|
end case;
|
425 |
|
|
end if;
|
426 |
|
|
end if;
|
427 |
|
|
end process pr_ctrl_ram;
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
------------------------------
|
431 |
|
|
--- Portmapping components ---
|
432 |
|
|
------------------------------
|
433 |
|
|
|
434 |
|
|
gen_generic_sp_ram : for i in 0 to 3 generate
|
435 |
|
|
begin
|
436 |
|
|
inst_generic_sp_ram : generic_sp_ram
|
437 |
|
|
generic map(
|
438 |
|
|
DISTR_RAM => DISTRIBUTED_RAM,
|
439 |
|
|
WORDS => MAX_WINDOW_LENGTH,
|
440 |
|
|
BITWIDTH => NUMBER_TRELLIS_STATES
|
441 |
|
|
)
|
442 |
|
|
port map(
|
443 |
|
|
clk => clk,
|
444 |
|
|
rst => rst,
|
445 |
|
|
wen => wen_ram(i),
|
446 |
|
|
en => en_ram(i),
|
447 |
|
|
a => std_logic_vector(addr(i)),
|
448 |
|
|
d => d,
|
449 |
|
|
q => q_reg(i)
|
450 |
|
|
);
|
451 |
|
|
end generate gen_generic_sp_ram;
|
452 |
|
|
|
453 |
|
|
end architecture rtl;
|