INFO: [Common 17-186] '/home/rafa/ufrgs/steel-core/vivado/steel-core.sim/sim_1/behav/xsim/xsim.dir/tb_compliance_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sat Oct 10 23:58:12 2020. For additional details about this file, please refer to the WebTalk help file at /home/rafa/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
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INFO: [Common 17-206] Exiting Webtalk at Sat Oct 10 23:58:12 2020...