URL
https://opencores.org/ocsvn/steelcore/steelcore/trunk
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| Line No. |
Rev |
Author |
Line |
| 1 |
11 |
rafaelcalc |
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/alu.v" into library xil_defaultlib
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| 2 |
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INFO: [VRFC 10-311] analyzing module alu
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| 3 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/branch_unit.v" into library xil_defaultlib
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| 4 |
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INFO: [VRFC 10-311] analyzing module branch_unit
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| 5 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/csr_file.v" into library xil_defaultlib
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| 6 |
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INFO: [VRFC 10-311] analyzing module csr_file
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| 7 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/decoder.v" into library xil_defaultlib
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| 8 |
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INFO: [VRFC 10-311] analyzing module decoder
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| 9 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/imm_generator.v" into library xil_defaultlib
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| 10 |
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INFO: [VRFC 10-311] analyzing module imm_generator
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| 11 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/integer_file.v" into library xil_defaultlib
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| 12 |
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INFO: [VRFC 10-311] analyzing module integer_file
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| 13 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/load_unit.v" into library xil_defaultlib
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| 14 |
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INFO: [VRFC 10-311] analyzing module load_unit
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| 15 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/machine_control.v" into library xil_defaultlib
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| 16 |
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INFO: [VRFC 10-311] analyzing module machine_control
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| 17 |
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INFO: [VRFC 10-2458] undeclared symbol FUNCT7_wfi, assumed default net type wire [/home/rafa/ufrgs/steel-core/rtl/machine_control.v:136]
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| 18 |
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INFO: [VRFC 10-2458] undeclared symbol RS2_ADDR_wfi, assumed default net type wire [/home/rafa/ufrgs/steel-core/rtl/machine_control.v:141]
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| 19 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/steel_top.v" into library xil_defaultlib
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| 20 |
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INFO: [VRFC 10-311] analyzing module steel_top
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| 21 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/store_unit.v" into library xil_defaultlib
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| 22 |
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INFO: [VRFC 10-311] analyzing module store_unit
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| 23 |
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/bench/tb_compliance.v" into library xil_defaultlib
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| 24 |
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INFO: [VRFC 10-311] analyzing module tb_compliance
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