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[/] [vivado/] [steel-core.srcs/] [sim_1/] [imports/] [steel-core/] [rtl/] [bench/] [tb_compliance.v] - Blame information for rev 11

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1 11 rafaelcalc 
//////////////////////////////////////////////////////////////////////////////////
2 
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
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//
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// Create Date: 30.07.2020 18:18:32
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// Module Name: tb_compliance
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// Project Name: Steel Core
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// Description: RISC-V compliance testbench
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//
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// Dependencies: globals.vh
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//               machine_control.v
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//               alu.v
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//               integer_file.v
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//               branch_unit.v
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//               decoder.v
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//               csr_file.v
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//               imm_generator.v
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//               load_unit.v
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//               store_unit.v
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//
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// Version 0.01
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//
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//////////////////////////////////////////////////////////////////////////////////
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24 
/*********************************************************************************
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26 
MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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37 
The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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`include "../globals.vh"
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53 
module tb_compliance();
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55 
    reg CLK;
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    reg RESET;
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    wire [31:0] I_ADDR;
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    reg [31:0] INSTR;
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    wire [31:0] D_ADDR;
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    wire [31:0] DATA_OUT;
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    wire WR_REQ;
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    wire [3:0] WR_MASK;
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    reg [31:0] DATA_IN;
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    reg E_IRQ;
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    reg T_IRQ;
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    reg S_IRQ;
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68 
    reg [8*50:0] tests [0:53] = {
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        "I-ADD-01.elf.mem",
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        "I-BLT-01.elf.mem",
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        "I-JAL-01.elf.mem",
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        "I-MISALIGN_JMP-01.elf.mem",
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        "I-SB-01.elf.mem",
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        "I-SRA-01.elf.mem",
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        "I-ADDI-01.elf.mem",
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        "I-BLTU-01.elf.mem",
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        "I-JALR-01.elf.mem",
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        "I-MISALIGN_LDST-01.elf.mem",
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        "I-SH-01.elf.mem",
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        "I-SRAI-01.elf.mem",
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        "I-AND-01.elf.mem",
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        "I-BNE-01.elf.mem",
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        "I-LB-01.elf.mem",
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        "I-NOP-01.elf.mem",
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        "I-SLL-01.elf.mem",
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        "I-SRL-01.elf.mem",
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        "I-ANDI-01.elf.mem",
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        "I-DELAY_SLOTS-01.elf.mem",
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        "I-LBU-01.elf.mem",
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        "I-OR-01.elf.mem",
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        "I-SLLI-01.elf.mem",
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        "I-SRLI-01.elf.mem",
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        "I-AUIPC-01.elf.mem",
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        "I-EBREAK-01.elf.mem",
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        "I-LH-01.elf.mem",
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        "I-ORI-01.elf.mem",
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        "I-SLT-01.elf.mem",
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        "I-SUB-01.elf.mem",
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        "I-BEQ-01.elf.mem",
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        "I-ECALL-01.elf.mem",
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        "I-LHU-01.elf.mem",
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        "I-RF_size-01.elf.mem",
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        "I-SLTI-01.elf.mem",
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        "I-SW-01.elf.mem",
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        "I-BGE-01.elf.mem",
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        "I-ENDIANESS-01.elf.mem",
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        "I-LUI-01.elf.mem",
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        "I-RF_width-01.elf.mem",
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        "I-SLTIU-01.elf.mem",
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        "I-XOR-01.elf.mem",
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        "I-BGEU-01.elf.mem",
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        "I-IO-01.elf.mem",
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        "I-LW-01.elf.mem",
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        "I-RF_x0-01.elf.mem",
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        "I-SLTU-01.elf.mem",
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        "I-XORI-01.elf.mem",
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        "I-CSRRC-01.elf.mem",
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        "I-CSRRCI-01.elf.mem",
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        "I-CSRRS-01.elf.mem",
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        "I-CSRRSI-01.elf.mem",
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        "I-CSRRW-01.elf.mem",
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        "I-CSRRWI-01.elf.mem"
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        };
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125 
    reg [8*256:0] signatures [0:53] = {
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        "../../../../../compliance/I-ADD-01.signature.output",
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        "../../../../../compliance/I-BLT-01.signature.output",
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        "../../../../../compliance/I-JAL-01.signature.output",
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        "../../../../../compliance/I-MISALIGN_JMP-01.signature.output",
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        "../../../../../compliance/I-SB-01.signature.output",
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        "../../../../../compliance/I-SRA-01.signature.output",
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        "../../../../../compliance/I-ADDI-01.signature.output",
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        "../../../../../compliance/I-BLTU-01.signature.output",
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        "../../../../../compliance/I-JALR-01.signature.output",
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        "../../../../../compliance/I-MISALIGN_LDST-01.signature.output",
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        "../../../../../compliance/I-SH-01.signature.output",
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        "../../../../../compliance/I-SRAI-01.signature.output",
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        "../../../../../compliance/I-AND-01.signature.output",
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        "../../../../../compliance/I-BNE-01.signature.output",
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        "../../../../../compliance/I-LB-01.signature.output",
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        "../../../../../compliance/I-NOP-01.signature.output",
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        "../../../../../compliance/I-SLL-01.signature.output",
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        "../../../../../compliance/I-SRL-01.signature.output",
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        "../../../../../compliance/I-ANDI-01.signature.output",
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        "../../../../../compliance/I-DELAY_SLOTS-01.signature.output",
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        "../../../../../compliance/I-LBU-01.signature.output",
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        "../../../../../compliance/I-OR-01.signature.output",
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        "../../../../../compliance/I-SLLI-01.signature.output",
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        "../../../../../compliance/I-SRLI-01.signature.output",
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        "../../../../../compliance/I-AUIPC-01.signature.output",
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        "../../../../../compliance/I-EBREAK-01.signature.output",
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        "../../../../../compliance/I-LH-01.signature.output",
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        "../../../../../compliance/I-ORI-01.signature.output",
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        "../../../../../compliance/I-SLT-01.signature.output",
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        "../../../../../compliance/I-SUB-01.signature.output",
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        "../../../../../compliance/I-BEQ-01.signature.output",
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        "../../../../../compliance/I-ECALL-01.signature.output",
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        "../../../../../compliance/I-LHU-01.signature.output",
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        "../../../../../compliance/I-RF_size-01.signature.output",
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        "../../../../../compliance/I-SLTI-01.signature.output",
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        "../../../../../compliance/I-SW-01.signature.output",
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        "../../../../../compliance/I-BGE-01.signature.output",
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        "../../../../../compliance/I-ENDIANESS-01.signature.output",
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        "../../../../../compliance/I-LUI-01.signature.output",
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        "../../../../../compliance/I-RF_width-01.signature.output",
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        "../../../../../compliance/I-SLTIU-01.signature.output",
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        "../../../../../compliance/I-XOR-01.signature.output",
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        "../../../../../compliance/I-BGEU-01.signature.output",
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        "../../../../../compliance/I-IO-01.signature.output",
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        "../../../../../compliance/I-LW-01.signature.output",
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        "../../../../../compliance/I-RF_x0-01.signature.output",
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        "../../../../../compliance/I-SLTU-01.signature.output",
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        "../../../../../compliance/I-XORI-01.signature.output",
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        "../../../../../compliance/I-CSRRC-01.signature.output",
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        "../../../../../compliance/I-CSRRCI-01.signature.output",
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        "../../../../../compliance/I-CSRRS-01.signature.output",
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        "../../../../../compliance/I-CSRRSI-01.signature.output",
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        "../../../../../compliance/I-CSRRW-01.signature.output",
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        "../../../../../compliance/I-CSRRWI-01.signature.output"
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        };
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    steel_top #(
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        .BOOT_ADDRESS(32'h00000000)
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        ) dut (
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        .CLK(CLK),
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        .RESET(RESET),
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        .REAL_TIME(64'b0),
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        .I_ADDR(I_ADDR),
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        .INSTR(INSTR),
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        .D_ADDR(D_ADDR),
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        .DATA_OUT(DATA_OUT),
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        .WR_REQ(WR_REQ),
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        .WR_MASK(WR_MASK),
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        .DATA_IN(DATA_IN),
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        .E_IRQ(E_IRQ),
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        .T_IRQ(T_IRQ),
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        .S_IRQ(S_IRQ)
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    );
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    reg [31:0] ram [0:16383]; // 4KB RAM
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    integer f;
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    integer i;
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    integer j;
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    integer k;
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    integer m;
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    integer n;
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212 
    always
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    begin
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        #10 CLK = !CLK;
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    end
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217 
    initial
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    begin
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220 
        for(k = 0; k < 54; k=k+1)
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        begin
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223 
            // LOADS PROGRAM INTO MEMORY
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            for(i = 0; i < 65535; i=i+1) ram[i] = 32'b0;
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            $display("Running %s...", tests[k]);
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            f = $fopen(signatures[k], "w");
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            $readmemh(tests[k],ram);
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            // INITIAL VALUES
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            RESET = 1'b0;
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            CLK = 1'b0;
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            E_IRQ = 1'b0;
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            T_IRQ = 1'b0;
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            S_IRQ = 1'b0;
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            // RESET
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            #5;
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            RESET = 1'b1;
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            #15;
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            RESET = 1'b0;
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242 
            // one second loop
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            for(j = 0; j < 50000000; j = j + 1)
244 
            begin
245 
                #20;
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                if(WR_REQ == 1'b1 && D_ADDR == 32'h00001000)
247 
                begin
248 
                    m = ram[2047][16:2];
249 
                    n = ram[2046][16:2];
250 
                    for(m = ram[2047][16:2]; m < n; m=m+1)
251 
                    begin
252 
                        $fwrite(f, "%h\n", ram[m]);
253 
                        $display("%h", ram[m]);
254 
                    end
255 
                    #20;
256 
                    j = 50000000;
257 
                end
258 
            end
259 
 
260 
            $fclose(f);
261 
 
262 
        end
263 
 
264 
        $display("All signatures generated. Run the verify.sh script located inside the compliance folder.");
265 
 
266 
    end
267 
 
268 
    always @(posedge CLK or posedge RESET)
269 
    begin
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        if(RESET)
271 
        begin
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            INSTR = ram[I_ADDR[15:2]];
273 
            DATA_IN = ram[D_ADDR[15:2]];
274 
        end
275 
        else
276 
        begin
277 
            INSTR = ram[I_ADDR[15:2]];
278 
            DATA_IN = ram[D_ADDR[15:2]];
279 
            if(WR_REQ)
280 
            begin
281 
                if(WR_MASK[0])
282 
                begin
283 
                    ram[D_ADDR[15:2]][7:0] <= DATA_OUT[7:0];
284 
                end
285 
                if(WR_MASK[1])
286 
                begin
287 
                    ram[D_ADDR[15:2]][15:8] <= DATA_OUT[15:8];
288 
                end
289 
                if(WR_MASK[2])
290 
                begin
291 
                    ram[D_ADDR[15:2]][23:16] <= DATA_OUT[23:16];
292 
                end
293 
                if(WR_MASK[3])
294 
                begin
295 
                    ram[D_ADDR[15:2]][31:24] <= DATA_OUT[31:24];
296 
                end
297 
            end
298 
        end
299 
    end
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301 
endmodule
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