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mjlyons |
/*****************************************************************************
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* Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc_selftest.c
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* Version: 1.00.a
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* Description: Contains a diagnostic self-test function for the spiifc driver
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* Date: Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
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*****************************************************************************/
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/***************************** Include Files *******************************/
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#include "spiifc.h"
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/************************** Constant Definitions ***************************/
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/************************** Variable Definitions ****************************/
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extern Xuint32 LocalBRAM; /* User logic local memory (BRAM) base address */
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/************************** Function Definitions ***************************/
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/**
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*
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* Run a self-test on the driver/device. Note this may be a destructive test if
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* resets of the device are performed.
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*
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* If the hardware system is not built correctly, this function may never
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* return to the caller.
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*
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* @param baseaddr_p is the base address of the SPIIFC instance to be worked on.
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*
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* @return
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*
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* - XST_SUCCESS if all self-test code passed
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* - XST_FAILURE if any self-test code failed
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*
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* @note Caching must be turned off for this function to work.
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* @note Self test may fail if data memory and device are not on the same bus.
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*
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*/
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XStatus SPIIFC_SelfTest(void * baseaddr_p)
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{
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int Index;
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Xuint32 baseaddr;
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Xuint8 Reg8Value;
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Xuint16 Reg16Value;
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Xuint32 Reg32Value;
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Xuint32 Mem32Value;
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/*
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* Check and get the device address
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*/
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/*
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* Base Address maybe 0. Up to developer to uncomment line below.
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XASSERT_NONVOID(baseaddr_p != XNULL);
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*/
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baseaddr = (Xuint32) baseaddr_p;
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xil_printf("******************************\n\r");
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xil_printf("* User Peripheral Self Test\n\r");
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xil_printf("******************************\n\n\r");
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/*
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* Write to user logic slave module register(s) and read back
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*/
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xil_printf("User logic slave module test...\n\r");
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xil_printf(" - write 1 to slave register 0 word 0\n\r");
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SPIIFC_mWriteSlaveReg0(baseaddr, 0, 1);
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Reg32Value = SPIIFC_mReadSlaveReg0(baseaddr, 0);
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xil_printf(" - read %d from register 0 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 1 )
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{
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xil_printf(" - slave register 0 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 2 to slave register 1 word 0\n\r");
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SPIIFC_mWriteSlaveReg1(baseaddr, 0, 2);
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Reg32Value = SPIIFC_mReadSlaveReg1(baseaddr, 0);
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xil_printf(" - read %d from register 1 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 2 )
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{
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xil_printf(" - slave register 1 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 3 to slave register 2 word 0\n\r");
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SPIIFC_mWriteSlaveReg2(baseaddr, 0, 3);
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Reg32Value = SPIIFC_mReadSlaveReg2(baseaddr, 0);
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xil_printf(" - read %d from register 2 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 3 )
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{
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xil_printf(" - slave register 2 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 4 to slave register 3 word 0\n\r");
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SPIIFC_mWriteSlaveReg3(baseaddr, 0, 4);
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Reg32Value = SPIIFC_mReadSlaveReg3(baseaddr, 0);
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xil_printf(" - read %d from register 3 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 4 )
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{
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xil_printf(" - slave register 3 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 5 to slave register 4 word 0\n\r");
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SPIIFC_mWriteSlaveReg4(baseaddr, 0, 5);
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Reg32Value = SPIIFC_mReadSlaveReg4(baseaddr, 0);
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xil_printf(" - read %d from register 4 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 5 )
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{
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xil_printf(" - slave register 4 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 6 to slave register 5 word 0\n\r");
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SPIIFC_mWriteSlaveReg5(baseaddr, 0, 6);
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Reg32Value = SPIIFC_mReadSlaveReg5(baseaddr, 0);
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xil_printf(" - read %d from register 5 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 6 )
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{
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xil_printf(" - slave register 5 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 7 to slave register 6 word 0\n\r");
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SPIIFC_mWriteSlaveReg6(baseaddr, 0, 7);
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Reg32Value = SPIIFC_mReadSlaveReg6(baseaddr, 0);
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xil_printf(" - read %d from register 6 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 7 )
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{
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xil_printf(" - slave register 6 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 8 to slave register 7 word 0\n\r");
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SPIIFC_mWriteSlaveReg7(baseaddr, 0, 8);
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Reg32Value = SPIIFC_mReadSlaveReg7(baseaddr, 0);
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xil_printf(" - read %d from register 7 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 8 )
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{
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xil_printf(" - slave register 7 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 9 to slave register 8 word 0\n\r");
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SPIIFC_mWriteSlaveReg8(baseaddr, 0, 9);
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Reg32Value = SPIIFC_mReadSlaveReg8(baseaddr, 0);
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xil_printf(" - read %d from register 8 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 9 )
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{
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xil_printf(" - slave register 8 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 10 to slave register 9 word 0\n\r");
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SPIIFC_mWriteSlaveReg9(baseaddr, 0, 10);
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Reg32Value = SPIIFC_mReadSlaveReg9(baseaddr, 0);
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xil_printf(" - read %d from register 9 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 10 )
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{
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xil_printf(" - slave register 9 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 11 to slave register 10 word 0\n\r");
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SPIIFC_mWriteSlaveReg10(baseaddr, 0, 11);
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Reg32Value = SPIIFC_mReadSlaveReg10(baseaddr, 0);
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xil_printf(" - read %d from register 10 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 11 )
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{
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xil_printf(" - slave register 10 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 12 to slave register 11 word 0\n\r");
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SPIIFC_mWriteSlaveReg11(baseaddr, 0, 12);
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Reg32Value = SPIIFC_mReadSlaveReg11(baseaddr, 0);
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xil_printf(" - read %d from register 11 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 12 )
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{
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xil_printf(" - slave register 11 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 13 to slave register 12 word 0\n\r");
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SPIIFC_mWriteSlaveReg12(baseaddr, 0, 13);
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Reg32Value = SPIIFC_mReadSlaveReg12(baseaddr, 0);
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xil_printf(" - read %d from register 12 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 13 )
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{
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xil_printf(" - slave register 12 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 14 to slave register 13 word 0\n\r");
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SPIIFC_mWriteSlaveReg13(baseaddr, 0, 14);
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Reg32Value = SPIIFC_mReadSlaveReg13(baseaddr, 0);
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xil_printf(" - read %d from register 13 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 14 )
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{
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xil_printf(" - slave register 13 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 15 to slave register 14 word 0\n\r");
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SPIIFC_mWriteSlaveReg14(baseaddr, 0, 15);
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Reg32Value = SPIIFC_mReadSlaveReg14(baseaddr, 0);
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xil_printf(" - read %d from register 14 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 15 )
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{
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xil_printf(" - slave register 14 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - write 16 to slave register 15 word 0\n\r");
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SPIIFC_mWriteSlaveReg15(baseaddr, 0, 16);
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Reg32Value = SPIIFC_mReadSlaveReg15(baseaddr, 0);
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xil_printf(" - read %d from register 15 word 0\n\r", Reg32Value);
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if ( Reg32Value != (Xuint32) 16 )
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{
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xil_printf(" - slave register 15 word 0 write/read failed\n\r");
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return XST_FAILURE;
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}
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xil_printf(" - slave register write/read passed\n\n\r");
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/*
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* Write data to user logic BRAMs and read back
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*/
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xil_printf("User logic BRAM test...\n\r");
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xil_printf(" - local BRAM address is 0x%08x\n\r", LocalBRAM);
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xil_printf(" - write pattern to local BRAM and read back\n\r");
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for ( Index = 0; Index < 256; Index++ )
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{
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SPIIFC_mWriteMemory(LocalBRAM+4*Index, 0xDEADBEEF);
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Mem32Value = SPIIFC_mReadMemory(LocalBRAM+4*Index);
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if ( Mem32Value != 0xDEADBEEF )
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{
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xil_printf(" - write/read BRAM failed on address 0x%08x\n\r", LocalBRAM+4*Index);
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return XST_FAILURE;
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}
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}
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xil_printf(" - write/read BRAM passed\n\n\r");
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/*
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* Enable all possible interrupts and clear interrupt status register(s)
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*/
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xil_printf("Interrupt controller test...\n\r");
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Reg32Value = SPIIFC_mReadReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET);
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xil_printf(" - IP (user logic) interrupt status : 0x%08x\n\r", Reg32Value);
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xil_printf(" - clear IP (user logic) interrupt status register\n\r");
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SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET, Reg32Value);
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xil_printf(" - enable all possible interrupt(s)\n\r");
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SPIIFC_EnableInterrupt(baseaddr_p);
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xil_printf(" - write/read interrupt register passed\n\n\r");
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return XST_SUCCESS;
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}
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