URL https://opencores.org/ocsvn/vspi/vspi/trunk

Subversion Repositories vspi

[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [tb_fastclock.wcfg] - Blame information for rev 14

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      SPI_MISO
      SPI_MISO
   
   
      txMemAddr[11:0]
      txMemAddr[11:0]
      HEXRADIX
   
   
      txMemData[7:0]
      txMemData[7:0]
      HEXRADIX
   
   
      rcMemAddr[11:0]
      rcMemAddr[11:0]
      HEXRADIX
   
   
      rcMemData[7:0]
      rcMemData[7:0]
      HEXRADIX
   
   
      rcMemWE
      rcMemWE
   
   
      debug_out[7:0]
      debug_out[7:0]
      HEXRADIX
   
   
      Reset
      Reset
   
   
      SysClk
      SysClk
   
   
      SPI_CLK
      SPI_CLK
   
   
      SPI_MOSI
      SPI_MOSI
   
   
      SPI_SS
      SPI_SS
   
   
      SPI_CLK_en
      SPI_CLK_en
   
   
      fdRcBytes[31:0]
      fdRcBytes[31:0]
      HEXRADIX
   
   
      fdTxBytes[31:0]
      fdTxBytes[31:0]
      HEXRADIX
   
   
      dummy[31:0]
      dummy[31:0]
      HEXRADIX
   
   
      currRcByte[31:0]
      currRcByte[31:0]
      HEXRADIX
   
   
      rcBytesNotEmpty[31:0]
      rcBytesNotEmpty[31:0]
      HEXRADIX
   
   
      rcBytesStr[80:1]
      rcBytesStr[80:1]
      HEXRADIX
   
   
      label
      packetStart
      packetStart
      packetStart
   
   
      validSpiBit
      validSpiBit
   
   
      rcByteValid
      rcByteValid
   
   
      state[7:0]
      state[7:0]
      HEXRADIX
   
   
      state_reg[7:0]
      state_reg[7:0]
      HEXRADIX
   
   
      rcByteValid
      rcByteValid
   
   
      rcByte[7:0]
      rcByte[7:0]
      HEXRADIX
   
   
      txBitIndex[2:0]
      txBitIndex[2:0]
      HEXRADIX
   
   
      txBitIndex_reg[2:0]
      txBitIndex_reg[2:0]
      HEXRADIX
   
   
      txMemAddr[11:0]
      txMemAddr[11:0]
      HEXRADIX
   
   
      txMemData[7:0]
      txMemData[7:0]
      HEXRADIX
   


Line No.	Rev	Author	Line
1	14	mjlyons
2
3
4
5
6
7
8
9
10
11
12
13
14
15			`SPI_MISO`
16			`SPI_MISO`
17
18
19			`txMemAddr[11:0]`
20			`txMemAddr[11:0]`
21			`HEXRADIX`
22
23
24			`txMemData[7:0]`
25			`txMemData[7:0]`
26			`HEXRADIX`
27
28
29			`rcMemAddr[11:0]`
30			`rcMemAddr[11:0]`
31			`HEXRADIX`
32
33
34			`rcMemData[7:0]`
35			`rcMemData[7:0]`
36			`HEXRADIX`
37
38
39			`rcMemWE`
40			`rcMemWE`
41
42
43			`debug_out[7:0]`
44			`debug_out[7:0]`
45			`HEXRADIX`
46
47
48			`Reset`
49			`Reset`
50
51
52			`SysClk`
53			`SysClk`
54
55
56			`SPI_CLK`
57			`SPI_CLK`
58
59
60			`SPI_MOSI`
61			`SPI_MOSI`
62
63
64			`SPI_SS`
65			`SPI_SS`
66
67
68			`SPI_CLK_en`
69			`SPI_CLK_en`
70
71
72			`fdRcBytes[31:0]`
73			`fdRcBytes[31:0]`
74			`HEXRADIX`
75
76
77			`fdTxBytes[31:0]`
78			`fdTxBytes[31:0]`
79			`HEXRADIX`
80
81
82			`dummy[31:0]`
83			`dummy[31:0]`
84			`HEXRADIX`
85
86
87			`currRcByte[31:0]`
88			`currRcByte[31:0]`
89			`HEXRADIX`
90
91
92			`rcBytesNotEmpty[31:0]`
93			`rcBytesNotEmpty[31:0]`
94			`HEXRADIX`
95
96
97			`rcBytesStr[80:1]`
98			`rcBytesStr[80:1]`
99			`HEXRADIX`
100
101
102			`label`
103			`packetStart`
104			`packetStart`
105			`packetStart`
106
107
108			`validSpiBit`
109			`validSpiBit`
110
111
112			`rcByteValid`
113			`rcByteValid`
114
115
116			`state[7:0]`
117			`state[7:0]`
118			`HEXRADIX`
119
120
121			`state_reg[7:0]`
122			`state_reg[7:0]`
123			`HEXRADIX`
124
125
126			`rcByteValid`
127			`rcByteValid`
128
129
130			`rcByte[7:0]`
131			`rcByte[7:0]`
132			`HEXRADIX`
133
134
135			`txBitIndex[2:0]`
136			`txBitIndex[2:0]`
137			`HEXRADIX`
138
139
140			`txBitIndex_reg[2:0]`
141			`txBitIndex_reg[2:0]`
142			`HEXRADIX`
143
144
145			`txMemAddr[11:0]`
146			`txMemAddr[11:0]`
147			`HEXRADIX`
148
149
150			`txMemData[7:0]`
151			`txMemData[7:0]`
152			`HEXRADIX`
153
154

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Subversion Repositories vspi

[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [tb_fastclock.wcfg] - Blame information for rev 14