URL https://opencores.org/ocsvn/vspi/vspi/trunk

Subversion Repositories vspi

[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [tb_writereg.wcfg] - Blame information for rev 14

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      SPI_MISO
      SPI_MISO
   
   
      txMemAddr[11:0]
      txMemAddr[11:0]
      HEXRADIX
   
   
      rcMemAddr[11:0]
      rcMemAddr[11:0]
      HEXRADIX
   
   
      rcMemData[7:0]
      rcMemData[7:0]
      HEXRADIX
   
   
      rcMemWE
      rcMemWE
   
   
      debug_out[7:0]
      debug_out[7:0]
      HEXRADIX
   
   
      Reset
      Reset
   
   
      SysClk
      SysClk
   
   
      SPI_CLK
      SPI_CLK
   
   
      SPI_MOSI
      SPI_MOSI
   
   
      SPI_SS
      SPI_SS
   
   
      txMemData[7:0]
      txMemData[7:0]
      HEXRADIX
   
   
      SPI_CLK_en
      SPI_CLK_en
   
   
      fdRcBytes[31:0]
      fdRcBytes[31:0]
      HEXRADIX
   
   
      fdTxBytes[31:0]
      fdTxBytes[31:0]
      HEXRADIX
   
   
      dummy[31:0]
      dummy[31:0]
      HEXRADIX
   
   
      currRcByte[31:0]
      currRcByte[31:0]
      HEXRADIX
   
   
      rcBytesNotEmpty[31:0]
      rcBytesNotEmpty[31:0]
      HEXRADIX
   
   
      rcBytesStr[80:1]
      rcBytesStr[80:1]
      HEXRADIX
   
   
      regAddr[3:0]
      regAddr[3:0]
      HEXRADIX
   
   
      regReadData[31:0]
      regReadData[31:0]
      HEXRADIX
   
   
      regWriteEn
      regWriteEn
   
   
      regWriteData[31:0]
      regWriteData[31:0]
      HEXRADIX
   
   
      rcByteValid
      rcByteValid
   
   
      rcByte[7:0]
      rcByte[7:0]
      HEXRADIX
   
   
      state[7:0]
      state[7:0]
      HEXRADIX
   
   
      state_reg[7:0]
      state_reg[7:0]
      HEXRADIX
   
   
      command[7:0]
      command[7:0]
      HEXRADIX
   
   
      rcWordByteId[1:0]
      rcWordByteId[1:0]
      HEXRADIX
   
   
      rcWord[31:0]
      rcWord[31:0]
      HEXRADIX
   
   
      regReadByte_oreg[7:0]
      regReadByte_oreg[7:0]
      HEXRADIX
   
   
      txBitIndex[2:0]
      txBitIndex[2:0]
      HEXRADIX
   
   
      txBitIndex_reg[2:0]
      txBitIndex_reg[2:0]
      HEXRADIX
   


Line No.	Rev	Author	Line
1	14	mjlyons
2
3
4
5
6
7
8
9
10
11
12
13
14
15			`SPI_MISO`
16			`SPI_MISO`
17
18
19			`txMemAddr[11:0]`
20			`txMemAddr[11:0]`
21			`HEXRADIX`
22
23
24			`rcMemAddr[11:0]`
25			`rcMemAddr[11:0]`
26			`HEXRADIX`
27
28
29			`rcMemData[7:0]`
30			`rcMemData[7:0]`
31			`HEXRADIX`
32
33
34			`rcMemWE`
35			`rcMemWE`
36
37
38			`debug_out[7:0]`
39			`debug_out[7:0]`
40			`HEXRADIX`
41
42
43			`Reset`
44			`Reset`
45
46
47			`SysClk`
48			`SysClk`
49
50
51			`SPI_CLK`
52			`SPI_CLK`
53
54
55			`SPI_MOSI`
56			`SPI_MOSI`
57
58
59			`SPI_SS`
60			`SPI_SS`
61
62
63			`txMemData[7:0]`
64			`txMemData[7:0]`
65			`HEXRADIX`
66
67
68			`SPI_CLK_en`
69			`SPI_CLK_en`
70
71
72			`fdRcBytes[31:0]`
73			`fdRcBytes[31:0]`
74			`HEXRADIX`
75
76
77			`fdTxBytes[31:0]`
78			`fdTxBytes[31:0]`
79			`HEXRADIX`
80
81
82			`dummy[31:0]`
83			`dummy[31:0]`
84			`HEXRADIX`
85
86
87			`currRcByte[31:0]`
88			`currRcByte[31:0]`
89			`HEXRADIX`
90
91
92			`rcBytesNotEmpty[31:0]`
93			`rcBytesNotEmpty[31:0]`
94			`HEXRADIX`
95
96
97			`rcBytesStr[80:1]`
98			`rcBytesStr[80:1]`
99			`HEXRADIX`
100
101
102			`regAddr[3:0]`
103			`regAddr[3:0]`
104			`HEXRADIX`
105
106
107			`regReadData[31:0]`
108			`regReadData[31:0]`
109			`HEXRADIX`
110
111
112			`regWriteEn`
113			`regWriteEn`
114
115
116			`regWriteData[31:0]`
117			`regWriteData[31:0]`
118			`HEXRADIX`
119
120
121			`rcByteValid`
122			`rcByteValid`
123
124
125			`rcByte[7:0]`
126			`rcByte[7:0]`
127			`HEXRADIX`
128
129
130			`state[7:0]`
131			`state[7:0]`
132			`HEXRADIX`
133
134
135			`state_reg[7:0]`
136			`state_reg[7:0]`
137			`HEXRADIX`
138
139
140			`command[7:0]`
141			`command[7:0]`
142			`HEXRADIX`
143
144
145			`rcWordByteId[1:0]`
146			`rcWordByteId[1:0]`
147			`HEXRADIX`
148
149
150			`rcWord[31:0]`
151			`rcWord[31:0]`
152			`HEXRADIX`
153
154
155			`regReadByte_oreg[7:0]`
156			`regReadByte_oreg[7:0]`
157			`HEXRADIX`
158
159
160			`txBitIndex[2:0]`
161			`txBitIndex[2:0]`
162			`HEXRADIX`
163
164
165			`txBitIndex_reg[2:0]`
166			`txBitIndex_reg[2:0]`
167			`HEXRADIX`
168
169

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Subversion Repositories vspi

[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [tb_writereg.wcfg] - Blame information for rev 14