URL
https://opencores.org/ocsvn/vspi/vspi/trunk
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
14 |
mjlyons |
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"
|
| 2 |
|
|
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
|
| 3 |
|
|
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
|
| 4 |
|
|
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
|
| 5 |
|
|
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
|
| 6 |
|
|
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
|
| 7 |
|
|
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
|
| 8 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd"
|
| 9 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd"
|
| 10 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd"
|
| 11 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd"
|
| 12 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd"
|
| 13 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd"
|
| 14 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd"
|
| 15 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd"
|
| 16 |
|
|
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd"
|
| 17 |
|
|
vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd"
|
| 18 |
|
|
verilog spiifc_v1_00_a "../../hdl/verilog/user_logic.v"
|
| 19 |
|
|
vhdl spiifc_v1_00_a "../../hdl/vhdl/spiifc.vhd"
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.