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mjlyons |
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# Makefile generated by Xilinx Platform Studio
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# Project:C:\Users\mjlyons\workspace\vSPI\projnav\xps\system.xmp
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#
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# WARNING : This file will be re-generated every time a command
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# to run a make target is invoked. So, any changes made to this
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# file manually, will be lost when make is invoked next.
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#################################################################
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# Name of the Microprocessor system
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# The hardware specification of the system is in file :
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# C:\Users\mjlyons\workspace\vSPI\projnav\xps\system.mhs
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include system_incl.make
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#################################################################
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# PHONY TARGETS
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#################################################################
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.PHONY: dummy
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.PHONY: netlistclean
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.PHONY: bitsclean
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.PHONY: simclean
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.PHONY: exporttosdk
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#################################################################
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# EXTERNAL TARGETS
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#################################################################
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all:
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@echo "Makefile to build a Microprocessor system :"
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@echo "Run make with any of the following targets"
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@echo " "
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@echo " netlist : Generates the netlist for the given MHS "
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@echo " bits : Runs Implementation tools to generate the bitstream"
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@echo " exporttosdk: Export files to SDK"
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@echo " "
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@echo " init_bram: Initializes bitstream with BRAM data"
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@echo " ace : Generate ace file from bitstream and elf"
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@echo " download : Downloads the bitstream onto the board"
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@echo " "
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@echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
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@echo " simmodel : Generates HDL simulation models for chosen simulation mode"
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@echo " "
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@echo " netlistclean: Deletes netlist"
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@echo " bitsclean: Deletes bit, ncd, bmm files"
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@echo " hwclean : Deletes implementation dir"
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@echo " simclean : Deletes simulation dir"
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@echo " clean : Deletes all generated files/directories"
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@echo " "
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bits: $(SYSTEM_BIT)
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ace: $(SYSTEM_ACE)
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exporttosdk: $(SYSTEM_HW_HANDOFF_DEP)
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netlist: $(POSTSYN_NETLIST)
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download: $(DOWNLOAD_BIT) dummy
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@echo "*********************************************"
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@echo "Downloading Bitstream onto the target board"
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@echo "*********************************************"
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impact -batch etc/download.cmd
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init_bram: $(DOWNLOAD_BIT)
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sim: $(DEFAULT_SIM_SCRIPT)
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cd simulation/behavioral & \
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system_fuse.cmd
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cd simulation/behavioral & \
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start /B $(SIM_CMD) -gui -tclbatch system_setup.tcl
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simmodel: $(DEFAULT_SIM_SCRIPT)
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behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
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structural_model: $(STRUCTURAL_SIM_SCRIPT)
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clean: hwclean simclean
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rm -f _impact.cmd
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hwclean: netlistclean bitsclean
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rm -rf implementation synthesis xst hdl
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rm -rf xst.srp $(SYSTEM).srp
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rm -f __xps/ise/_xmsgs/bitinit.xmsgs
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netlistclean:
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rm -f $(POSTSYN_NETLIST)
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rm -f platgen.log
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rm -f __xps/ise/_xmsgs/platgen.xmsgs
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rm -f $(BMM_FILE)
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bitsclean:
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rm -f $(SYSTEM_BIT)
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rm -f implementation/$(SYSTEM).ncd
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rm -f implementation/$(SYSTEM)_bd.bmm
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rm -f implementation/$(SYSTEM)_map.ncd
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rm -f implementation/download.bit
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rm -f __xps/$(SYSTEM)_routed
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simclean:
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rm -rf simulation/behavioral
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rm -f simgen.log
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rm -f __xps/ise/_xmsgs/simgen.xmsgs
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#################################################################
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# BOOTLOOP ELF FILES
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#################################################################
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$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP)
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IF NOT EXIST "$(BOOTLOOP_DIR)" @mkdir "$(BOOTLOOP_DIR)"
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cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP)
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#################################################################
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# HARDWARE IMPLEMENTATION FLOW
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#################################################################
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$(BMM_FILE) \
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$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
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$(CORE_STATE_DEVELOPMENT_FILES)
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@echo "****************************************************"
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@echo "Creating system netlist for hardware specification.."
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@echo "****************************************************"
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platgen $(PLATGEN_OPTIONS) $(MHSFILE)
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$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
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@echo "Running synthesis..."
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cd synthesis & synthesis.cmd
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__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)
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@echo "*********************************************"
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@echo "Running Xilinx Implementation tools.."
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@echo "*********************************************"
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@cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
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@cp -f etc/fast_runtime.opt implementation/xflow.opt
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xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc
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touch __xps/$(SYSTEM)_routed
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$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE)
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xilperl $(XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par
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@echo "*********************************************"
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@echo "Running Bitgen.."
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@echo "*********************************************"
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@cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
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cd implementation & bitgen -w -f bitgen.ut $(SYSTEM) & cd ..
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$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_IMP_FILES) __xps/bitinit.opt
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@cp -f implementation/$(SYSTEM)_bd.bmm .
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@echo "*********************************************"
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@echo "Initializing BRAM contents of the bitstream"
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@echo "*********************************************"
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bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_IMP_FILE_ARGS) \
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-bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
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@rm -f $(SYSTEM)_bd.bmm
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$(SYSTEM_ACE):
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@echo "In order to generate ace file, you must have:-"
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@echo "- exactly one processor."
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@echo "- opb_mdm, if using microblaze."
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#################################################################
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# EXPORT_TO_SDK FLOW
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#################################################################
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$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt
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IF NOT EXIST "$(SDK_EXPORT_DIR)" @mkdir "$(SDK_EXPORT_DIR)"
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psf2Edward -inp $(SYSTEM).xmp -exit_on_error -edwver 1.2 -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT)
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$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT)
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@rm -rf $(SYSTEM_HW_HANDOFF_BIT)
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@cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR)
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$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm
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@rm -rf $(SYSTEM_HW_HANDOFF_BMM)
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@cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR)
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#################################################################
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# SIMULATION FLOW
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#################################################################
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################## BEHAVIORAL SIMULATION ##################
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$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
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$(BRAMINIT_ELF_SIM_FILES)
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@echo "*********************************************"
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@echo "Creating behavioral simulation models..."
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@echo "*********************************************"
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simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
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################## STRUCTURAL SIMULATION ##################
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$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
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$(BRAMINIT_ELF_SIM_FILES)
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@echo "*********************************************"
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@echo "Creating structural simulation models..."
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@echo "*********************************************"
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simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
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################## TIMING SIMULATION ##################
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implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed
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$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \
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$(BRAMINIT_ELF_SIM_FILES)
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@echo "*********************************************"
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@echo "Creating timing simulation models..."
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@echo "*********************************************"
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simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
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dummy:
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@echo ""
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