URL
https://opencores.org/ocsvn/vtach/vtach/trunk
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
wd5gnr |
CoreGen has not been configured with any user repositories.
|
| 2 |
|
|
CoreGen has been configured with the following Xilinx repositories:
|
| 3 |
|
|
- '/opt/Xilinx/13.2/ISE_DS/ISE/coregen/' [using existing xil_index.xml]
|
| 4 |
|
|
INFO:encore:314 - Created non-GUI application for batch mode execution.
|
| 5 |
|
|
Wrote CGP file for project 'coregen'.
|
| 6 |
|
|
INFO:sim - Generating component instance 'icon_pro' of
|
| 7 |
|
|
'xilinx.com:ip:chipscope_icon:1.05.a' from
|
| 8 |
|
|
'/opt/Xilinx/13.2/ISE_DS/ISE/coregen/iprepo/Chipscope/pcores/chipscope_icon_v
|
| 9 |
|
|
1_05_a/chipscope_icon_v1_05_a.xcd'.
|
| 10 |
|
|
Resolving generic values...
|
| 11 |
|
|
Finished resolving generic values.
|
| 12 |
|
|
Generating IP...
|
| 13 |
|
|
Gathering HDL files for icon_pro root...
|
| 14 |
|
|
Creating XST project for icon_pro...
|
| 15 |
|
|
Creating XST script file for icon_pro...
|
| 16 |
|
|
Creating XST instantiation file for icon_pro...
|
| 17 |
|
|
Running XST for icon_pro...
|
| 18 |
|
|
XST: HDL Compilation
|
| 19 |
|
|
XST: Design Hierarchy Analysis
|
| 20 |
|
|
XST: HDL Analysis
|
| 21 |
|
|
XST: HDL Synthesis
|
| 22 |
|
|
XST: Advanced HDL Synthesis
|
| 23 |
|
|
XST: Low Level Synthesis
|
| 24 |
|
|
Generating VHDL wrapper
|
| 25 |
|
|
Not generating Verilog wrapper
|
| 26 |
|
|
Creating ISE instantiation template for icon_pro...
|
| 27 |
|
|
Skipping Verilog instantiation template for icon_pro...
|
| 28 |
|
|
Finished Generation.
|
| 29 |
|
|
Generating IP instantiation template...
|
| 30 |
|
|
Generating metadata file...
|
| 31 |
|
|
Generating ISE project...
|
| 32 |
|
|
Generating README file...
|
| 33 |
|
|
Generating FLIST file...
|
| 34 |
|
|
INFO:sim - Finished FLIST file generation.
|
| 35 |
|
|
Moving files to output directory...
|
| 36 |
|
|
Finished moving files to output directory
|
| 37 |
|
|
Saved CGP file for project 'coregen'.
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.