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# Xilinx Core Generator version 13.2

# Date: Sun May 19 14:49:36 2013

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

#  Generated from component: xilinx.com:ip:chipscope_icon:1.05.a

#

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#

# BEGIN Project Options

SET addpads = false

SET asysymbol = false

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = false

SET designentry = VHDL

SET device = xc3s50

SET devicefamily = spartan3

SET flowvendor = Other

SET formalverification = false

SET foundationsym = false

SET implementationfiletype = Ngc

SET package = pq208

SET removerpms = false

SET simulationfiles = Structural

SET speedgrade = -5

SET verilogsim = false

SET vhdlsim = true

# END Project Options

# BEGIN Select

SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.05.a

# END Select

# BEGIN Parameters

CSET component_name=icon_pro

CSET enable_jtag_bufg=true

CSET example_design=false

CSET number_control_ports=1

CSET use_ext_bscan=false

CSET use_softbscan=false

CSET use_unused_bscan=false

CSET user_scan_chain=USER1

# END Parameters

GENERATE

# CRC: 39a6dc52