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[/] [vtach/] [trunk/] [_ngo/] [cs_ila_pro_0/] [coregen.cgc] - Blame information for rev 2

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   xilinx.com
   CoreGen
   coregen
   1.0
   
      
         ila_pro_0
         
         
            ila_pro_0
            1
            1
            1
            1
            basic
            basic
            basic
            basic
            1
            basic
            1
            basic
            1
            basic
            1
            true
            1
            1
            1
            basic_with_edges
            basic
            basic
            basic
            1
            basic
            1
            basic
            1
            basic
            1
            basic
            1
            basic
            1
            1
            1
            Rising
            Disabled
            Disabled
            true
            Disabled
            Disabled
            Disabled
            Disabled
            0
            Disabled
            false
            true
            1
            1
            1
            1
            1
            1
            16
            1
            512
            1
            1
            Disabled
            Disabled
            Disabled
            Disabled
            false
            Disabled
            false
            Disabled
            false
            false
            Disabled
            false
            false
            Disabled
            false
            false
            Disabled
            false
            false
            false
            false
            false
            false
            false
            false
            9
            1
            1
            1
            1
            false
            false
            false
            0
            1
            0
            0
            16
            1
            0
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            1
            0
            0
            6
            0
            12
            1
            1
            1
            1
            1
            1
            1
            1
            9
            1
            0
            0
            7
            13
            1
            1
            1
            2
            1
            false
            1
            1
            1
            1
            1
            1
            1
            1
            1
            0
            1
            1
            0
            0
            0
            1
            1
            8
            14
            0
            1
            1
            3
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            9
            ila_pro_0
            15
            0
            Component_Name=ila_pro_0;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=16;Use_RPMs=true;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=512;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=9;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=1;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=1;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=1;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=1;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=1;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=1;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=1;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=1;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=1;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=1;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=1;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=1;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=1;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=1;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=1;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic;Exclude_From_Data_Storage_16=false
            4
            10
            1
            1
            0
            0
            512
            1
            2
            0
            1
            0
            0
            0
            1
            5
            0
            0
            11
            0
            0
            0
            0
            1
            0
            1
            0
            1
            0
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc3s50
                  spartan3
                  pq208
                  -5
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  false
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Structural
                  VHDL
                  false
               
            
            
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./ila_pro_0.xco
                     xco
                     Sun May 19 14:50:24 GMT 2013
                     0xCD21F3E5
                     generationid_2213806706
                  
               
               
                  ngc_netlist_generator
                  
                     ./ila_pro_0.cdc
                     unknown
                     Sun May 19 14:51:26 GMT 2013
                     0xC344A1A0
                     generationid_2213806706
                  
                  
                     ./ila_pro_0.ngc
                     ngc
                     Sun May 19 14:51:26 GMT 2013
                     0x3E7D882C
                     generationid_2213806706
                  
                  
                     ./ila_pro_0.vhd
                     vhdl
                     Sun May 19 14:51:22 GMT 2013
                     0x0F3CBC0C
                     generationid_2213806706
                  
                  
                     ./ila_pro_0.vho
                     vho
                     Sun May 19 14:51:22 GMT 2013
                     0x13864C8F
                     generationid_2213806706
                  
               
               
                  instantiation_template_generator
                  
                     ./ila_pro_0.vho
                     vho
                     Sun May 19 14:51:26 GMT 2013
                     0x13864C8F
                     generationid_2213806706
                  
               
               
                  asy_generator
               
               
                  xmdf_generator
                  
                     ./ila_pro_0_xmdf.tcl
                     tclXmdf
                     tcl
                     Sun May 19 14:51:26 GMT 2013
                     0x5AFCC3BC
                     generationid_2213806706
                  
               
               
                  ise_generator
                  
                     ./ila_pro_0.gise
                     ignore
                     gise
                     Sun May 19 14:51:29 GMT 2013
                     0x085AEC12
                     generationid_2213806706
                  
                  
                     ./ila_pro_0.xise
                     ignore
                     xise
                     Sun May 19 14:51:29 GMT 2013
                     0x0247B23B
                     generationid_2213806706
                  
               
               
                  deliver_readme_generator
                  
                     ./ila_pro_0_readme.txt
                     ignore
                     txtReadme
                     txt
                     Sun May 19 14:51:29 GMT 2013
                     0x8C356996
                     generationid_2213806706
                  
               
               
                  flist_generator
                  
                     ./ila_pro_0_flist.txt
                     ignore
                     txtFlist
                     txt
                     Sun May 19 14:51:29 GMT 2013
                     0xF4EE8665
                     generationid_2213806706
                  
               
            
         
      
   
   
      
         
            coregen
            ./
            ./tmp/
            ./tmp/_cg/
         
         
            xc6vcx75t
            virtex6
            ff484
            -2
         
         
            BusFormatAngleBracketNotRipped
            VHDL
            true
            Other
            false
            false
            false
            Ngc
            false
         
         
            Behavioral
            VHDL
            false
         
      
   

 

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Subversion Repositories vtach

[/] [vtach/] [trunk/] [_ngo/] [cs_ila_pro_0/] [coregen.cgc] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	wd5gnr
2
3			`xilinx.com`
4			`CoreGen`
5			`coregen`
6			`1.0`
7
8
9			`ila_pro_0`
10
11
12			`ila_pro_0`
13			`1`
14			`1`
15			`1`
16			`1`
17			`basic`
18			`basic`
19			`basic`
20			`basic`
21			`1`
22			`basic`
23			`1`
24			`basic`
25			`1`
26			`basic`
27			`1`
28			`true`
29			`1`
30			`1`
31			`1`
32			`basic_with_edges`
33			`basic`
34			`basic`
35			`basic`
36			`1`
37			`basic`
38			`1`
39			`basic`
40			`1`
41			`basic`
42			`1`
43			`basic`
44			`1`
45			`basic`
46			`1`
47			`1`
48			`1`
49			`Rising`
50			`Disabled`
51			`Disabled`
52			`true`
53			`Disabled`
54			`Disabled`
55			`Disabled`
56			`Disabled`
57			`0`
58			`Disabled`
59			`false`
60			`true`
61			`1`
62			`1`
63			`1`
64			`1`
65			`1`
66			`1`
67			`16`
68			`1`
69			`512`
70			`1`
71			`1`
72			`Disabled`
73			`Disabled`
74			`Disabled`
75			`Disabled`
76			`false`
77			`Disabled`
78			`false`
79			`Disabled`
80			`false`
81			`false`
82			`Disabled`
83			`false`
84			`false`
85			`Disabled`
86			`false`
87			`false`
88			`Disabled`
89			`false`
90			`false`
91			`false`
92			`false`
93			`false`
94			`false`
95			`false`
96			`false`
97			`9`
98			`1`
99			`1`
100			`1`
101			`1`
102			`false`
103			`false`
104			`false`
105			`0`
106			`1`
107			`0`
108			`0`
109			`16`
110			`1`
111			`0`
112			`1`
113			`0`
114			`0`
115			`0`
116			`0`
117			`0`
118			`0`
119			`0`
120			`0`
121			`0`
122			`0`
123			`1`
124			`0`
125			`0`
126			`6`
127			`0`
128			`12`
129			`1`
130			`1`
131			`1`
132			`1`
133			`1`
134			`1`
135			`1`
136			`1`
137			`9`
138			`1`
139			`0`
140			`0`
141			`7`
142			`13`
143			`1`
144			`1`
145			`1`
146			`2`
147			`1`
148			`false`
149			`1`
150			`1`
151			`1`
152			`1`
153			`1`
154			`1`
155			`1`
156			`1`
157			`1`
158			`0`
159			`1`
160			`1`
161			`0`
162			`0`
163			`0`
164			`1`
165			`1`
166			`8`
167			`14`
168			`0`
169			`1`
170			`1`
171			`3`
172			`1`
173			`0`
174			`0`
175			`0`
176			`0`
177			`0`
178			`0`
179			`0`
180			`0`
181			`0`
182			`0`
183			`0`
184			`0`
185			`0`
186			`0`
187			`0`
188			`0`
189			`0`
190			`0`
191			`0`
192			`9`
193			`ila_pro_0`
194			`15`
195			`0`
196			Component_Name=ila_pro_0;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=16;Use_RPMs=true;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=512;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=9;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=1;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=1;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=1;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=1;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=1;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=1;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=1;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=1;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=1;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=1;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=1;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=1;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=1;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=1;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=1;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic;Exclude_From_Data_Storage_16=false
197			`4`
198			`10`
199			`1`
200			`1`
201			`0`
202			`0`
203			`512`
204			`1`
205			`2`
206			`0`
207			`1`
208			`0`
209			`0`
210			`0`
211			`1`
212			`5`
213			`0`
214			`0`
215			`11`
216			`0`
217			`0`
218			`0`
219			`0`
220			`1`
221			`0`
222			`1`
223			`0`
224			`1`
225			`0`
226			`0`
227			`0`
228			`0`
229			`0`
230			`0`
231			`0`
232
233
234
235
236			`coregen`
237			`./`
238			`./tmp/`
239			`./tmp/_cg/`
240
241
242			`xc3s50`
243			`spartan3`
244			`pq208`
245			`-5`
246
247
248			`BusFormatAngleBracketNotRipped`
249			`VHDL`
250			`false`
251			`Other`
252			`false`
253			`false`
254			`false`
255			`Ngc`
256			`false`
257
258
259			`Structural`
260			`VHDL`
261			`false`
262
263
264
265
266			`model_parameter_resolution_generator`
267
268
269			`ip_xco_generator`
270
271			`./ila_pro_0.xco`
272			`xco`
273			`Sun May 19 14:50:24 GMT 2013`
274			`0xCD21F3E5`
275			`generationid_2213806706`
276
277
278
279			`ngc_netlist_generator`
280
281			`./ila_pro_0.cdc`
282			`unknown`
283			`Sun May 19 14:51:26 GMT 2013`
284			`0xC344A1A0`
285			`generationid_2213806706`
286
287
288			`./ila_pro_0.ngc`
289			`ngc`
290			`Sun May 19 14:51:26 GMT 2013`
291			`0x3E7D882C`
292			`generationid_2213806706`
293
294
295			`./ila_pro_0.vhd`
296			`vhdl`
297			`Sun May 19 14:51:22 GMT 2013`
298			`0x0F3CBC0C`
299			`generationid_2213806706`
300
301
302			`./ila_pro_0.vho`
303			`vho`
304			`Sun May 19 14:51:22 GMT 2013`
305			`0x13864C8F`
306			`generationid_2213806706`
307
308
309
310			`instantiation_template_generator`
311
312			`./ila_pro_0.vho`
313			`vho`
314			`Sun May 19 14:51:26 GMT 2013`
315			`0x13864C8F`
316			`generationid_2213806706`
317
318
319
320			`asy_generator`
321
322
323			`xmdf_generator`
324
325			`./ila_pro_0_xmdf.tcl`
326			`tclXmdf`
327			`tcl`
328			`Sun May 19 14:51:26 GMT 2013`
329			`0x5AFCC3BC`
330			`generationid_2213806706`
331
332
333
334			`ise_generator`
335
336			`./ila_pro_0.gise`
337			`ignore`
338			`gise`
339			`Sun May 19 14:51:29 GMT 2013`
340			`0x085AEC12`
341			`generationid_2213806706`
342
343
344			`./ila_pro_0.xise`
345			`ignore`
346			`xise`
347			`Sun May 19 14:51:29 GMT 2013`
348			`0x0247B23B`
349			`generationid_2213806706`
350
351
352
353			`deliver_readme_generator`
354
355			`./ila_pro_0_readme.txt`
356			`ignore`
357			`txtReadme`
358			`txt`
359			`Sun May 19 14:51:29 GMT 2013`
360			`0x8C356996`
361			`generationid_2213806706`
362
363
364
365			`flist_generator`
366
367			`./ila_pro_0_flist.txt`
368			`ignore`
369			`txtFlist`
370			`txt`
371			`Sun May 19 14:51:29 GMT 2013`
372			`0xF4EE8665`
373			`generationid_2213806706`
374
375
376
377
378
379
380
381
382
383			`coregen`
384			`./`
385			`./tmp/`
386			`./tmp/_cg/`
387
388
389			`xc6vcx75t`
390			`virtex6`
391			`ff484`
392			`-2`
393
394
395			`BusFormatAngleBracketNotRipped`
396			`VHDL`
397			`true`
398			`Other`
399			`false`
400			`false`
401			`false`
402			`Ngc`
403			`false`
404
405
406			`Behavioral`
407			`VHDL`
408			`false`
409
410
411
412
413