URL
https://opencores.org/ocsvn/vtach/vtach/trunk
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wd5gnr |
CoreGen has not been configured with any user repositories.
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CoreGen has been configured with the following Xilinx repositories:
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- '/opt/Xilinx/13.2/ISE_DS/ISE/coregen/' [using existing xil_index.xml]
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INFO:encore:314 - Created non-GUI application for batch mode execution.
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Wrote CGP file for project 'coregen'.
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INFO:sim - Generating component instance 'ila_pro_0' of
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'xilinx.com:ip:chipscope_ila:1.04.a' from
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'/opt/Xilinx/13.2/ISE_DS/ISE/coregen/iprepo/Chipscope/pcores/chipscope_ila_v1
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_04_a/chipscope_ila_v1_04_a.xcd'.
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Resolving generic values...
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Finished resolving generic values.
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Generating IP...
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| 13 |
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Gathering HDL files for ila_pro_0 root...
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Creating XST project for ila_pro_0...
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| 15 |
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Creating XST script file for ila_pro_0...
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Creating XST instantiation file for ila_pro_0...
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Running XST for ila_pro_0...
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XST: HDL Compilation
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XST: Design Hierarchy Analysis
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XST: HDL Analysis
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XST: HDL Synthesis
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XST: Advanced HDL Synthesis
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XST: Low Level Synthesis
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Generating VHDL wrapper
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Not generating Verilog wrapper
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Creating ISE instantiation template for ila_pro_0...
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Skipping Verilog instantiation template for ila_pro_0...
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| 28 |
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Finished Generation.
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| 29 |
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Generating IP instantiation template...
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| 30 |
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Generating metadata file...
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Generating ISE project...
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| 32 |
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Generating README file...
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| 33 |
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Generating FLIST file...
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INFO:sim - Finished FLIST file generation.
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| 35 |
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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