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https://opencores.org/ocsvn/vtach/vtach/trunk
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wd5gnr |
#ChipScope Core Generator Project File Version 3.0
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#Sun May 19 09:51:26 CDT 2013
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SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8
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SignalExport.bus<0000>.name=TRIG0
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SignalExport.bus<0000>.offset=0.0
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SignalExport.bus<0000>.precision=0
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SignalExport.bus<0000>.radix=Bin
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SignalExport.bus<0000>.scaleFactor=1.0
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SignalExport.clockChannel=CLK
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SignalExport.dataEqualsTrigger=true
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SignalExport.triggerChannel<0000><0000>=TRIG0[0]
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SignalExport.triggerChannel<0000><0001>=TRIG0[1]
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SignalExport.triggerChannel<0000><0002>=TRIG0[2]
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SignalExport.triggerChannel<0000><0003>=TRIG0[3]
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SignalExport.triggerChannel<0000><0004>=TRIG0[4]
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SignalExport.triggerChannel<0000><0005>=TRIG0[5]
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SignalExport.triggerChannel<0000><0006>=TRIG0[6]
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SignalExport.triggerChannel<0000><0007>=TRIG0[7]
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SignalExport.triggerChannel<0000><0008>=TRIG0[8]
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SignalExport.triggerPort<0000>.name=TRIG0
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SignalExport.triggerPortCount=1
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SignalExport.triggerPortIsData<0000>=true
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SignalExport.triggerPortWidth<0000>=9
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SignalExport.type=ila
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