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-------------------------------------------------------------------------------

-- Copyright (c) 2013 Xilinx, Inc.

-- All Rights Reserved

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--   ____  ____

--  /   /\/   /

-- /___/  \  /    Vendor     : Xilinx

-- \   \   \/     Version    : 13.2

--  \   \         Application: XILINX CORE Generator

--  /   /         Filename   : ila_pro_0.vhd

-- /___/   /\     Timestamp  : Sun May 19 09:51:22 CDT 2013

-- \   \  /  \

--  \___\/\___\

--

-- Design Name: VHDL Synthesis Wrapper

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-- This wrapper is used to integrate with Project Navigator and PlanAhead

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY ila_pro_0 IS

  port (

    CONTROL: inout std_logic_vector(35 downto 0);

    CLK: in std_logic;

    TRIG0: in std_logic_vector(8 downto 0));

END ila_pro_0;

ARCHITECTURE ila_pro_0_a OF ila_pro_0 IS

BEGIN

END ila_pro_0_a;