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-------------------------------------------------------------------------------

-- Copyright (c) 2013 Xilinx, Inc.

-- All Rights Reserved

-------------------------------------------------------------------------------

--   ____  ____

--  /   /\/   /

-- /___/  \  /    Vendor     : Xilinx

-- \   \   \/     Version    : 13.2

--  \   \         Application: Xilinx CORE Generator

--  /   /         Filename   : ila_pro_0.vho

-- /___/   /\     Timestamp  : Sun May 19 09:51:22 CDT 2013

-- \   \  /  \

--  \___\/\___\

--

-- Design Name: ISE Instantiation template

-- Component Identifier: xilinx.com:ip:chipscope_ila:1.04.a

-------------------------------------------------------------------------------

-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

component ila_pro_0

  PORT (

    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);

    CLK : IN STD_LOGIC;

    TRIG0 : IN STD_LOGIC_VECTOR(8 DOWNTO 0));

end component;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : ila_pro_0

  port map (

    CONTROL => CONTROL,

    CLK => CLK,

    TRIG0 => TRIG0);

-- INST_TAG_END ------ End INSTANTIATION Template ------------